Tomoaki Kawamura

Advanced ATM-layer function MCM-D module for ATM wide-area network

This paper describes a high-performance and cost-effective MCM-D module for an ATM-layer function device. The MCM-D module is fabricated on a Si-substrate using the stacking RAM technique to reduce module size. The MCM has a 4-layer Si substrate, a high-performance ASIC, 8 high-speed SRAMs, and an FPGA. By using the stacking RAM technique, MCM-D module size was reduced to 50.8 mm/spl times/50.8 mm. This is 40% of that (100 mm/spl times/65 mm) of a double-side mounted sub-board module with conventional packaging (QFP and SOP). The MCM-D module realizes the ATM-layer functions that require a high-performance ASIC with high-speed (access time 20 ns) and large-capacity (1 MBytes) SRAM cache. The MCM approach is quite effective in increasing memory access speed because it realizes high-density packaging. The MCM-D module was mounted on an ATM line interface circuit, and realized 150 Mbit/s throughput ATM-layer functions (header conversion and on-line monitoring) in an ATM switching system. In addition, advanced ATM-WAN (wide-area network) switching system hardware technologies with sub-module structure are also described. The MCM-D module is one of the sub-modules of the system. This MCM technology and sub-module technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.

Advanced ATM switching system hardware technology using MCM-D, stacking RAM microprocessor module

This paper describes newly developed advanced ATM switching system hardware structures based on MCM-D microprocessor modules. The Si-substrate MCM-D technology which integrates microprocessor, interface control and peripheral control custom VLSIs, high-speed SRAMs, and FPGAs is employed. An MCM-D microprocessor module is realized by combining a Motorola 68030, high-performance ASICs, and high-speed SRAM caches. This is made possible by high density packaging and high-speed 4M-byte with parity cache using 25 ns access to 4-Mbit of SRAM memory. The MCM employs 12 SRAMs, possible with the stacked RAM technique, to reduce the module size by 7/8 compared to conventional surface mounting modules. This microprocessor module technology and MCM technology will advance the development of practical B-ISDN ATM switching systems.

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs

A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10Gb/s. The issues focused on here are not only the data rate, which is eight times higher than that of a conventional GE-PON, but also the instantaneous amplification and synchronization of AC-coupling burst-input data without a reset signal. An input amplifier with data-edge detection can both detect levelvarying input due to AC-coupling and respond to the first bit of a burst packet. Another issue discussed here is tolerance to long consecutive identical digits (CIDs). A burst-mode clock-and-data recovery (CDR) using dual gated VCOs (G-VCOs) is designed for 10-Gb/s operation. The relation between the frequency difference of the dual G-VCOs and CID tolerance is derived with a frequency tunable G-VCO circuit. The burst-mode CDR IC is implemented in a 0.13-μm CMOS process. It successfully operates at a data rate of 10.3125Gb/s. The CDR IC using the edge-detection input amplifier and the G-VCO CDR core achieves amplification and synchronization in 0.2ns with AC-coupling without a reset signal. The IC also demonstrates 1001bits of CID tolerance, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet. Measured data suggest that dual G-VCOs on a die have over a 20-MHz frequency difference and that the frequency adjusting between the G-VCOs is effective for increasing CID tolerance.

Advanced MCM-D micro-processor module for ATM wide-area network switching systems

This paper describes an advanced MCM-D microprocessor module and its high-performance cooling technologies for an ATM-WAN (wide area network) switching system. The MCM-D is fabricated on 2 Si-substrates using the stacking RAM technique to reduce module size. The MCM has 4-layer Si substrates, a microprocessor LSI, 4 ASIC-LSIs, 12 high-speed SRAMs, an FPGA and bus-driver ICs. By using the stacking RAM technique, MCM-D size was reduced to 63 mm/spl times/85 mm. This is 14% of the assembly area (200 mm/spl times/200 mm) of a conventional circuit using conventional packaging technologies. The MCM-D was mounted on an ATM line interface circuit board, and realized 25 MHz microprocessor functions with high-speed (access time 25 ns) and large-capacity (4 MBytes) SRAM cache and ATM line interface circuit functions in an ATM-WAN switching system. The line interface circuit board-mounted MCM-D has a high-performance cooling architecture without fin structure. The MCM-D module is mounted on a sub-board and has thermal contact to the main board through a rubber spacer with low thermal resistance. By using this high-performance cooling architecture, the MCM-D microprocessor module and the ATM line interface circuit board operate under conventional forced air cooling conditions without a fin structure. This MCM technology and high-performance cooling technology can be applied to ATM-WAN switching systems and future B-ISDN ATM switching systems.

An MCM-D module using newly structured thermal management technique

This paper describes a newly developed MCM-D microprocessor module for advanced ATM switching systems. The Si-substrate MCM-D technology, which integrates a Motorola 68030 microprocessor, interface control, and peripheral control custom VLSIs, high-speed SRAMs and FPGAs (field programmable gate arrays), is employed. This is made possible by high density packaging with the stacked high-speed RAM technique, and reduces module size by 7/8 compared to conventional surface mounting schemes. In addition, a uniquely structured thermal management technique is employed. MCM heat flows to the printed motherboard power supply layer through via holes. Using this technique, module volume can be dramatically reduced. This microprocessor module technology and MCM technology has been developed to advance the development of practical B-ISDN ATM switching systems.

Development of plastic chip scale package for ATM switching systems

A plastic chip-scale package (CSP) smaller than conventional packages has been developed and applied to ATM switching systems. The package uses a low-cost glass-epoxy substrate. As glass epoxy is widely used in the printed circuit boards (PCBs) of ATM switching systems, its use in the CSPs mounted on a PCB reduces the difference in thermal expansion between PCB and CSPs, thus lengthening CSP life. The power plane, ground plane, and thermal vias of the CSP are designed to offset the increased thermal resistance due to the CSPs smaller size. Simulation showed a thermal resistance for this CSP with copper layers and thermal vias of as much as 22% less than that of a CSP with no copper layers or thermal vias. A six-layer test board mounting four CSPs was used to simulate a sub-board for ATM switching systems. The thermal resistance of the two CSPs located downstream was about 10% higher than that of the two located upstream. Two CSPs were developed for two types of application-specific ICs: a bus interface controller (BIC) and a peripheral interface circuit (PIC). Both CSPs were 18 mm square with a 0.8 mm outer solder-ball pitch and 256 outer balls. These CSPs occupied areas about 87% and 68% smaller than those of a conventional pin grid array (PGA) and quad flat package (QFP) respectively. The junction temperature of both CSPs satisfied the thermal conditions. These high-performance CSPs are thus attractive for use in ATM switching systems.