Tomoji Nakamura

Advantages of thermal nitride and nitroxide gate films in VLSI process

Thin gate SiO2films thinner than 200 Å often deteriorate throughout developmental VLSI processes, including refractory metal or silicide gates and ion- or plasma-assisted processes. Thermal nitridation of such SiO2films improves the MOS characteristics by producing surface protective layers against impurity penetration and by producing good interfacial characteristics. This fact indicates that a thermally grown silicon nitride film on a silicon substrate is the most promising candidate for a very-thin gate insulator. Experimental data show significant benefits from the nitride film for future VLSI devices.

A normally-off type buried channel MOSFET for VLSI circuits

This paper presents the performance of a buried channel MOSFET (BC-MOSFET) that uses the bulk region as the conducting channel in contrast with the surface channel of the conventional device. Normally-off characteristic has been realized with the p-type silicon gate and the ion-implanted n-channel layer. Fabricated short channel BC-MOSFETs with the gate lengths of 1-3 µ have shown a small shift of threshold voltage with changing the gate length or drain bias. These devices also have high carrier mobility of 750 cm2/v.s and high breakdown voltage compared with those of the conventional device. Minimum delay time of 180 ps was obtained with a 13 stage ring oscillator which was constructed with 1 µ BC-MOSFET.

Development of sub 10-µm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory

200-mm and 300-mm device wafers were successfully thinned down to less than 10-µm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-µm, switching charge showed no change by the thinning process. CMOS logic device wafers thinned to 7-µm indicated neither change in Ion current nor junction leakage current. Thinning such wafers to <10-µm will allow for lower aspect ratio less than 4 of Through-Silicon-Via (TSV) in a via-last process.

A new leakage mechanism of Co salicide and optimized process conditions [for CMOS]

We have clarified a new leakage mechanism in Co salicide process for the ultrashallow junctions of 0.1-/spl mu/m CMOS devices and revealed the optimum Co salicide process conditions for minimizing the leakage current. We found that leakage currents flow from many localized points that are randomly distributed in the function area. We successfully verified our localized leakage model via Monte Carlo simulation. We identified abnormal CoSi/sub x/ spikes under the Co silicide film, as being the origin of the localized leakage current. These CoSi/sub x/ spikes grow rapidly only during annealing between 400 and 450/spl deg/C for 30 s when Co/sub 2/Si phase is formed. These spikes never grow during annealing at over 500/spl deg/C, and decrease with high temperature annealing. A minimum leakage current results by optimized annealing at between 800 and 850/spl deg/C for 30 s. This is because a trade-off exists between reducing the CoSi/sub x/ spikes and preventing the Co atom diffusion from Co silicide film to Si substrate, which begins at annealing above 900/spl deg/C.

An ultrahigh vacuum scanning tunneling microscope with a new inchworm mechanism

An ultrahigh vacuum scanning tunneling microscope (STM) with a new piezo‐driven inchworm for coarse positioning has been designed and constructed. The inchworm consists of five piezoelectric stacks and moves, being pressed from the side by a spring. This structure makes it durable to bakeout of the vacuum chamber. The tip and the sample set in the tunneling unit are exchangable without breaking vacuum. The STM chamber is attached to a conventional molecular beam epitaxy chamber equipped with surface analysis instruments without external vibration isolation. We have ascertained that the STM has an atomic‐order resolution even under poor conditions, where much acoustic noise and mechanical vibration are produced by vacuum pumps and cooling water in the main chamber.

Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects

Influence of the sidewall roughness in through-silicon via (TSV) on leakage currents has been studied. Micro steps along the sidewall, so-called scalloping, formed by Bosch etching, are strongly related to leakage currents between adjacent TSVs. Microcracks in the SiON barriers were observed by TEM analysis and correlated with the sidewall roughness. FEM simulations of the stress concentration along the sidewall roughness clarified the origin of cracking. A non-Bosch etching process showed smooth sidewall surface and we consider it to be feasible for reliable TSV interconnects.

Vacancy-type defects in electroplated Cu films probed by using a monoenergetic positron beam

Positron annihilation was used to probe vacancy-type defects in electroplated Cu films. Doppler broadening spectra of the annihilation radiation for Cu films deposited on samples with a Ta(20 nm)/SiO2(100 nm)/Si structure were measured with a monoenergetic positron beam. For an as-deposited Cu film, the line-shape parameter S measured 20 days after deposition was larger than that measured 1 day after deposition. The observed increase in the value of S was attributed to grain growth at room temperature and the corresponding increase in the fraction of positrons trapped by vacancy clusters in the grains. In isochronal annealing experiments, the value of S for an electroplated Cu film increased for annealing below 200 °C, suggesting agglomeration of vacancy-type defects (vacancy clusters). A decrease in the S value was observed for annealing above 300 °C, and this was attributed mainly to the decrease in the concentration of vacancy clusters. The annealing stages of the defects in electroplated Cu were found...

Computer analysis of a short-channel BC MOSFET

This paper describes the results of a two-dimensional numerical analysis of a normally-off-type buried-channel MOSFET (BC MOSFET). This device has two operation modes whose boundary is a flat-band voltage. Bulk current is a main current when V_{SG} . Short-channel effects, like the decrease of a threshold voltage, were examined. Devices with a thinner gate oxide, a shallower channel depth, and a higher substrate concentration are effective for the short-channel effect.

Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7- µm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors. It was found that the electrical properties were not affected by bonding, thinning and debonding process indicating good feasibility of 3D stacking integration to the strain and low-k technology.

Defects introduced into electroplated Cu films during room-temperature recrystallization probed by a monoenergetic positron beam

Positron annihilation was used to probe vacancy-type defects in electroplated Cu films deposited on Ta∕SiO2∕Si. Doppler broadening spectra of the annihilation radiation were measured for the Cu films during grain growth at room temperature (i.e., self-annealing). The line-shape parameter S increased during self-annealing, and the observed time dependence of S was well described by the Johnson-Mehl-Avrami-Kolmogorov kinetics. After self-annealing, the values of S were found to be larger than the S value for annealed pure Cu, suggesting that the positrons annihilated from the trapped state by vacancy-type defects in grains. From a comparison with the results of previous isochronal annealing experiments, the major species of defects introduced during self-annealing was found to be vacancy clusters. The size of these defects increased, but their concentration decreased, with increasing film thickness. In thicker Cu films, an enhanced flow of atoms and subsequent rapid grain growth cause such defect behavior.