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Featured researches published by Tomomasa Ueda.


international electron devices meeting | 2004

Improvement of robustness against write disturbance by novel cell design for high density MRAM

T. Kai; Masatoshi Yoshikawa; Masahiko Nakayama; Yoshiaki Fukuzumi; Toshihiko Nagase; Eiji Kitagawa; Tomomasa Ueda; Tatsuya Kishi; Sumio Ikegawa; Yoshiaki Asao; Kenji Tsuchida; Hiroaki Yoda; N. Ishiwata; Hiromitsu Hada; S. Tahara

A new bit cell designed to have an excellent astroid is presented from the viewpoints of both theory and experiment. The switching mechanism is unique. The robustness against the disturbance of half-selected bits is improved. Its excellent astroid improves thermal stability and has the potential to achieve extremely high density magnetoresistive random access memory (MRAM).


Journal of Applied Physics | 2005

Bit yield improvement by precise control of stray fields from SAF pinned layers for high-density MRAMs

Masatoshi Yoshikawa; T. Kai; Minoru Amano; Eiji Kitagawa; Toshihiko Nagase; Masahiko Nakayama; Shigeki Takahashi; Tomomasa Ueda; Tatsuya Kishi; Kenji Tsuchida; Sumio Ikegawa; Yoshiaki Asao; Hiroaki Yoda; Yoshiaki Fukuzumi; Kiyokazu Nagahara; Hideaki Numata; Hiromitsu Hada; Nobuyuki Ishiwata; S. Tahara

A write-operating window with a 100% functional bit yield was successfully obtained by the control of stray fields from synthetic antiferromagnetic (SAF) pinned layers in conventional magnetic random access memories with rectangular magnetic tunneling junction bits. The stray fields were controlled by a newly developed ion-beam etching technique without causing damage and by a precise setting of the SAF pinned layer thickness, and are balanced with Neel coupling fields. As a result, it was found that symmetric switching astroid curves with no offset were obtained and switching distributions were minimized at the zero offset field.


international electron devices meeting | 2004

Design and process integration for high-density, high-speed, and low-power 6F/sup 2/ cross point MRAM cell

Yoshiaki Asao; Minoru Amano; Hisanori Aikawa; Tomomasa Ueda; Tatsuya Kishi; Sumio Ikegawa; Kenji Tsuchida; Hiroaki Yoda; T. Kajiyama; Yoshiaki Fukuzumi; Yoshihisa Iwata; Akihiro Nitayama; K. Shimura; Y. Kato; S. Miura; N. Ishiwata; Hiromitsu Hada; S. Tahara

A cross point (CP) cell with hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) based in Y. Shimizu et al. (2004). The new CP cell has a potential high density of 6F/sup 2/ and a faster access time than the conventional CP cell. A cell layout design to realize 6F is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 /spl mu/m CMOS technology and 0.24/spl times/0.48 /spl mu/m/sup 2/ magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.


SID Symposium Digest of Technical Papers | 2011

4.1: Low-Temperature-Processed IGZO TFTs for Flexible AMOLED with Integrated Gate Driver Circuits

Kentaro Miura; Tomomasa Ueda; Shintaro Nakano; Nobuyoshi Saito; Yujiro Hara; Keiji Sugi; Tatsunori Sakano; Hajime Yamaguchi; Isao Amemiya; Keiko Akimoto; Hisashi Kameoka; Junichi Tonotani

We have reduced threshold voltage shift of IGZO TFTs processed at 200°C under bias-temperature stress of Vg = 20 V at 70°C for 2000 s to 0.22 V by optimizing IGZO deposition and annealing conditions. A flexible AMOLED display with integrated gate driver circuits has been demonstrated.


ieee international magnetics conference | 2006

Ion-Beam-Etched Profile Control of MTJ Cells for Improving the Switching Characteristics of High-Density MRAM

Shigeki Takahashi; Tadashi Kai; Naoharu Shimomura; Tomomasa Ueda; Minoru Amano; Masatoshi Yoshikawa; Eiji Kitagawa; Yoshiaki Asao; Sumio Ikegawa; Tatsuya Kishi; Hiroaki Yoda; Kiyokazu Nagahara; Tomonori Mukai; Hiromitsu Hada

The effect of the reduction of the sidewall redeposition layer of magnetic materials is investigated for submicron-patterned magnetic random access memory (MRAM) cells. The sidewall redeposition layer is made at the first etch step of a magnetic tunnel junction (MTJ) with ion beam etching (IBE) in the case that the sidewall angle of a hard mask is steep. By controlling the etched profile at the time of the first IBE step, formation of the redeposition layer is prevented. Functional test results of 1-Kb MRAM arrays show that the sidewall redeposition layer enlarges fluctuation of switching current, and reduces the write operation region. The effect of the sidewall redeposition on the switching characteristics of MRAM arrays is explained qualitatively by micromagnetic simulation solving the Landau-Lifshitz-Gilbert (LLG) equation


Japanese Journal of Applied Physics | 2010

Effect of Self-Heating on Time-Dependent Dielectric Breakdown in Ultrathin MgO Magnetic Tunnel Junctions for Spin Torque Transfer Switching Magnetic Random Access Memory

Keiji Hosotani; Makoto Nagamine; Tomomasa Ueda; Hisanori Aikawa; Sumio Ikegawa; Yoshiaki Asao; Hiroaki Yoda; Akihiro Nitayama

Spin torque transfer switching magnetic random access memory (Spin-MRAM) using MgO-magnetic tunnel junction (MTJ) is considered to be the most promising candidate for high-density, high-speed, and non-volatile RAM. Notwithstanding its excellent potential, the breakdown mechanism of MgO-MTJ has not been well understood although a thorough understanding is essential for commercialization of Spin-MRAM. In this paper, we demonstrate for the first time the modeling of dielectric breakdown phenomena of MgO-MTJ by time-dependent dielectric breakdown (TDDB) measurement concerning the effect of self-heating using simulation and conclude that E-model with the effect of self-heating at MgO-MTJ during current stress (power) removed gives the best fitting as a degradation model of MgO-MTJ ultrathin dielectrics.


ieee international magnetics conference | 2006

Magnetic and Writing Properties of Clad Lines Used in a Toggle MRAM

Kenichi Shimura; Norikazu Ohshima; Sadahiko Miura; Ryusuke Nebashi; Toshiyasu Suzuki; Hiromitsu Hada; S. Tahara; Hisanori Aikawa; Tomomasa Ueda; Takeshi Kajiyama; H. Yoda

We fabricated toggle magnetic random access memories with clad writing lines. First, we evaluated the structures and magnetic properties of sputter-deposited cladding layers. The substrate bias during the deposition affected not only the sidewall coverage, but also the crystallinity and magnetic properties of the cladding. The optimized clad lines reduced the writing current to as low as 50% of that of unclad lines. Moreover, the writing current deviation divided by the average current of magnetic tunnel junction cells with clad lines was as low as that with unclad lines. Using the optimized clad lines, we constructed memory arrays with a large operating margin and reduced switching current


ieee international magnetics conference | 2006

Switching Current Fluctuation and Repeatability for MRAM With Propeller-Shape MTJ

Naoharu Shimomura; Hiroaki Yoda; Sumio Ikegawa; T. Kai; Minoru Amano; Hisanori Aikawa; Tomomasa Ueda; Masahiko Nakayama; Yoshiaki Asao; Keiji Hosotani; Yuui Shimizu; Kenji Tsuchida

The writing region and the repeatability of the function test and switching current fluctuation of magnetoresistive random access memory (MRAM) with a propeller shape magnetic tunnel junction (MTJ) array is evaluated. The effect of the write sequence is also investigated. The writing region is larger when the easy-axis field pulse is turned on prior to the hard-axis field than that in the case of the opposite sequence. However, the total margin in the latter sequence is larger after the repeated tests because of the smaller switching field fluctuation. The average 1-sigma value of the switching field fluctuation is 1.7%, which is mainly caused by the thermal fluctuation. The probability of the write error is estimated to be less than 10-16 by the bit line writing region and the thermal stability


Journal of Applied Physics | 2007

Estimation of spin transfer torque effect and thermal activation effect on magnetization reversal in CoFeB∕MgO∕CoFeB magnetoresistive tunneling junctions

Masatoshi Yoshikawa; Tomomasa Ueda; Hisanori Aikawa; Naoharu Shimomura; Eiji Kitagawa; Masahiko Nakayama; Tadashi Kai; Katsuya Nishiyama; Toshihiko Nagase; Tatsuya Kishi; Sumio Ikegawa; Hiroaki Yoda

In the CoFeB∕MgO∕CoFeB magnetoresistive tunneling junctions, the bias-dependent magnetic switching curves are investigated and the spin transfer torque effect and the thermal activation effect on the magnetic switching are estimated. The different switching behaviors at the positive and negative biases were observed, which are the asymmetric changes of the coercive force and the shift field. In order to investigate the asymmetric reduction of the coercive force according to the bias direction, the magnetic excitation effect due to the hot electron was introduced. Consequently, from the analysis by using the current versus magnetic field phase diagram, the asymmetric reduction of the coercive force at the positive and negative biases was explained quantitatively by the relationship between the thermal activation effect due to the Joule heating and the magnetic excitation effect due to the hot electron.


IEEE Transactions on Magnetics | 2006

1.8 V Power Supply 16 Mb-MRAMs With 42.3% Array Efficiency

Hiroaki Yoda; Tadashi Kai; Tsuneo Inaba; Yoshihisa Iwata; Naoharu Shimomura; Sumio Ikegawa; Kenji Tsuchida; Yoshiaki Asao; Tatsuya Kishi; Tomomasa Ueda; Shigeki Takahashi; Makoto Nagamine; Takeshi Kajiyama; Masatoshi Yoshikawa; Minoru Amano; Toshihiko Nagase; Keiji Hosotani; Masahiko Nakayama; Yuui Shimizu; Hisanori Aikawa; Katsuya Nishiyama; Eiji Kitagawa; Ryousuke Takizawa; Yoshihiro Ueda; Masayoshi Iwayama; Kiyotaro Itagaki

Technologies for realizing high density MRAM were developed. First, new circuitry to lower the resistance of programming wires was developed. Second, both MTJ plane shape and cross-sectional structure were optimized to lower the programming current. Based on these two technologies, 16 Mb MRAM was designed, fabricated with 130 nm CMOS process and 240 nm back end MTJ process. As a result, a 1.8 V power supply MRAM with 42.3% array efficiency was successfully demonstrated

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