Tomoyuki Arai

Highly uniform InAlAs-InGaAs HEMT technology for high-speed optical communication system ICs

The authors have developed a highly uniform, InP-based high-electron-mobility transistor (HEMT) technology for high-speed optical communication system integrated circuits (ICs). Special attention was paid to obtaining a high yield and uniformity without degrading the high-frequency characteristics of these HEMTs. An InP etch-stopper layer was employed to control the gate recess etching. The authors successfully fabricated InAlAs-InGaAs HEMTs with a cutoff frequency of 175 GHz after interconnection, which is sufficiently high for application in 40-Gb/s optical communication ICs. The standard deviation of the threshold voltage was only 13 mV across a 3-in wafer. They also developed a fabrication process for a Y-shaped gate to maintain high uniformity, enabling us to integrate more than a thousand transistors with a 0.1-/spl mu/m-class gate length. With this technology, ICs with over 1000 transistors were successfully fabricated and operated at over 40 Gb/s. Furthermore, the authors fabricated a 2:1 multiplexer that had more than 200 transistors and reached an operating speed of 90 Gb/s. They have thus concluded that their InAlAs-InGaAs HEMT technology can be applied to fabricate high-speed ICs for optical communication systems.

Suppression of drain conductance in InP-based HEMTs by eliminating hole accumulation

We have developed planar-type InP-based high-electron mobility transistors (HEMTs) that significantly suppress the frequency dispersion of drain conductance (g/sub d/) and the kink phenomena, and have examined the physical mechanisms of these phenomena. These phenomena appear to be caused by hole accumulation at the extrinsic source due to impact ionization. Our planar structure includes alloyed ohmic contacts that eliminate the hole barrier at the interface between the carrier-supply layer and the channel in the source and drain region to suppress hole accumulation. Therefore, the planar structure effectively eliminated hole accumulation at the extrinsic source, and suppressed g/sub d/ frequency dispersion to 25% and the kink phenomena to 50% compared with conventional structure HEMTs.

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1-3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with baud-rate architecture [1] has been successfully operated at 56Gb/s, but additional components such as eye-monitoring comparators, phase detectors, and clock recovery circuitry as well as a power-efficient transmitter are needed to build a complete transceiver.

NiAuGeAu ohmic contacts for a planar InP-based high electron mobility transistor structure with suppressed drain conductance frequency dispersion

We have fabricated a thermally stable low-contact-resistance Ni/AuGe/Au contact metal for InP-based high electron mobility transistors (HEMTs) without a heavily doped cap layer. The contact resistance is strongly influenced by the amount of Ni. Minimum contact resistance of 0.19 Ω mm was obtained from a Ni (1 nm)/AuGe (50 nm)/Au (99 nm) contact annealed at 300 °C for 5 min in N2. A smooth surface was obtained after contact formation and excellent thermal stability was achieved during isothermal annealing at 350 °C for 1 h in a N2 ambient. This alloyed ohmic contact satisfies the requirements for device fabrication process steps after the ohmic contact formation. It prevents hole accumulation by eliminating the hole barrier at the carrier-supply layer/channel interface. It also suppresses the kink phenomena and drain conductance frequency dispersion of InP-based HEMTs, and therefore will greatly facilitate the fabrication of ultrahigh-speed integrated circuits.

Elimination of kink phenomena and drain current hysteresis in InP-based HEMTs with a direct ohmic structure

We eliminated kink phenomena and Ids hysteresis in a double-doped InP-based HEMT without degrading its frequency performance by fabricating direct ohmic contacts in the InGaAs channel. A direct ohmic structure lets us control current paths in the device and relax the electric field at the recess edge of the drain side. As a result, we can suppress impact ionization and decrease the hole currents that originate from the high electric field region at the recess edge of the drain side. Kink phenomena are eliminated in the direct ohmic structure. We also suggest a hole trap mechanism to explain the appearance of hysteresis in the I-V characteristic of the conventional nonalloyed ohmic structure device.

A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS

A low-power and area optimized 28-nm CMOS 28-Gb/s transceiver is presented. The transceiver comprised with one PLL shared with 4 transceiver lanes. To meet the CEI-28G-VSR and CAUI4 (chip-to-module) standards, a 1-tap DFE is employed for the receiver. The power reduction is realized by employing 1-tap loop unrolled DFE circuits with domino logic and dynamic latches, and eliminating FFE. The transceiver occupies 2.31 mm2 and consumes 505 mW (4.5 pJ/bit).

Suppressing the 1/f noise and noise figure of InP-based high electron mobility transistors

We have developed InP-based high electron mobility transistors (HEMTs) with a structure that significantly suppresses the 1/f noise, noise figure (NF), and drain conductance (gd) dispersion. These phenomena appear to be caused by the accumulation of holes that are generated by strong electric fields and accumulate at the extrinsic source because of the hole barrier at the carrier-supply-layer/channel interface. Our planar structure has alloyed ohmic contacts that suppress hole accumulation by eliminating the strong electric field and hole barrier at the carrier-supply-layer/channel interface. The 1/f noise and NF of InP-based HEMTs with this planar structure are therefore respectively 15 and 10 dB less than the 1/f noise and NF of InP-based HEMTs with the conventional structure.

A 7GHz wideband self-correcting quadrature VCO

A 4.0 to 6.6GHz self-correcting quadrature voltage controlled oscillator (QVCO) with phase compensation loop is implemented in a 65nm CMOS process. The topology couples IQ oscillation signals of two LC-VCOs, a phase shifter, and buffers with circular configuration. This paper introduces the idea to obtain low phase noise and accurate IQ phase quadrature oscillation signal, by employing phase compensation loop to correct the IQ phase error. The self-correcting QVCO achieves the IQ phase error less than a degree, and 1MHz offset phase noise -107dBc/Hz at 6.9GHz.

Suppression of drain conductance frequency dispersion in InP-based HEMTs by eliminating hole accumulation

InP-based HEMTs are promising devices for large-capacity optical fiber communication systems. To enable higher bit rate systems, though, drain conductance (g/sub d/) frequency dispersion must be suppressed as it causes jitter, which reduces the size of eye pattern openings in integrated circuits. We propose a planar structure device to remarkably suppress g/sub d/ frequency dispersion by eliminating hole accumulation at the extrinsic source. The band-discontinuity between the source contact and the channel was eliminated by direct ohmic contact, which increased the flow of holes to the source contact.