Tomoyuki Hirano

Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process

Novel channel-stress enhancement technology on damascene gate process with eSiGe S/D for pFET is demonstrated. It is found for the first time that the damascene gate process featured by the dummy gate removal is more effective in increasing channel strain than the gate-1st process as an embedded SiGe stressor technique is used. Furthermore, an additional channel recess related to the damascene process is shown to enhance channel strain, resulting in a 14% Ion improvement at Ioff = 100 nA/um. We propose combining these strain techniques with high-k/metal gate stacks for low-power and high-performance pFETs.

High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below

High-Performance Metal/High-

Newly proposed mobility-booster technologies are demonstrated for metal/high-k gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/HfO2 gate stacks with Tinv=1.4 nm on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using HfSix/HfO2 gate stacks with Tinv=1.4 nm. High-performance n- and pFETs are achieved with Ion=1300 and 1000 muA/mum at Ioff =100 nA/mum, Vdd=1.0 V, and a gate length of 40 nm, respectively.

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Extreme high-performance n- and pFETs are achieved as 1300 and 1000 uA/um at Ioff = 100 nA/um and Vdd = 1.0 V, respectively, by applying newly proposed booster technologies. The combination of top-cut dual-stress liners and damascene gate remarkably enhances channel stress especially for shorter gate lengths. High-Ion pFETs with compressive stress liners and embedded SiGe source/drain are performed by using ALD-TiN/HfO2 damascene gate stacks with Tinv = 1.4 nm on (100) substrates. On the other hand, nFETs with tensile stress liners are obtained by using HfSix/HfO2 damascene gate stacks with Tinv =1.4 nm.

n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

We have developed a dual metal gate CMOS technology with HfSi_x for nMOS and Ru for pMOS on HfO₂ gate dielectric. These gate stacks show high mobility (100% of universal mobility for electron, 80% for hole at high fields) down to T_inv of 1.7 nm and symmetrical low V_t equivalent to poly-Si/SiO₂. As a result, high drive currents of 780 muA/mum and 265 muA/mum at I_off = 1 nA/mum are achieved for V_dd = 1.0 V in L_g = 60 nm nMOS and pMOS, respectively We have applied the mobility enhancement technology to the Ru/HfO₂ pMOS by utilizing (110)-substrate. As a result, an excellent drive current of 400 muA/mum (151% improvement over (100)-p⁺poly-Si/SiO₂) is achieved

Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

We have experimentally shown that crystallization of HfO2 and the subsequent formation of fixed charges localized at the HfO2/SiO2 interface bring about a degradation of electron mobility. Systematic analyses of valence-band photoemission and transmission electron microscopy indicate that the oxygen transfer from the HfO2 layer to the Si substrate is promoted upon the crystallization of HfO2 and the fixed charges are generated during the process. These findings highlight the importance of controlling the crystallinity of HfO2 for realizing high performance metal gate high-κ field-effect transistors.

High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology

In this study, the potential of HfSiON as the node dielectric of deep-trench (DT) capacitors was investigated for the first time. It was found out that a uniform thickness and a uniform depth profile of each component in DT can be obtained by the ALD process which utilizes the catalytic effect of the Hf precursor and Si precursor. In addition, the mechanism underlying leakage current was analyzed and it was revealed that residual carbons in the film contribute to the Poole?Frenkel current through the film. On the basis of these findings, we propose the sequential high-pressure ozone treatment (SHO) and Al2O3/HfSiON/Si3N4 stack for DT applications. Finally, the DT capacitors of 65-nm-node embedded dynamic random-access memory (eDRAM) were fabricated and a capacitance enhancement of 50% from the conventional dielectric (NO) was obtained at the same leakage current.

Mechanism of Carrier Mobility Degradation Induced by Crystallization of HfO2 Gate Dielectrics

We have developed a high performance pMOSFET with ALD-TiN/HfO2 gate stacks on (110) substrate using gate last process at low temperature. High work function and low gate leakage current are obtained. An extremely high mobility equivalent to P+poly-Si/SiO2 on (110) substrate (171 cm2/Vs at 0.5 MV/cm) is achieved with ALD-TiN/HfO2 on (110) substrate in the thinner Tinv region of 1.7 nm. Vth roll-off characteristics are well controlled down to 50 nm. A high drive current of 380 uA/um at I off = 1 uA/um is achieved at Vdd = 1.0 V. The drive current of ALD-TiN/HfO2 gate stack on (110) substrate is improved 1.4 times compared with (100) substrate and 2.4 times compared with P+poly-Si/SiO2 on (100) substrate

Application of HfSiON to Deep-Trench Capacitors of Sub-45-nm-Node Embedded Dynamic Random-Access Memory

We propose a fluorine (F) treatment technique that is suitable for threshold voltage (Vth) modulation in p-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with the atomic layer deposition (ALD) TiN/HfO2 gate structure. A work function near the band edge is achieved using the F treatment technique without the degradation of hole mobility in PMOSFETs. Vth shift value is almost the same regardless of gate length. The barrier height shift attributable to the F treatment corresponds closely to the Vth shift. It is found that the F treatment technique modulates the effective work function. No Vth shift in n-channel MOSFET (NMOSFETs), namely, the ALD-TiN/HfSix/HfO2 gate stack structure, is observed with F treatment. It is confirmed that F treatment is a suitable technique for complementary MOSFET (CMOSFETs) due to the confinement of Vth shift only to PMOSFETs.

High Performance pMOSFET with ALD-TiN/HfO2 Gate Stack on (110) Substrate by Low Temperature Process

Systematic characterization of Hf–Si/HfO2 gate stacks revealed two mobility degradation modes. One is carrier scattering by fixed charges and/or trapped charges induced by the crystallization in the thick HfO2 case (inversion oxide thickness, Tinv> 1.6 nm). The other is the Hf penetration into the interfacial layer with the Si substrate in the thin HfO2 case (Tinv< 1.6 nm) for the Hf-rich electrode. It was demonstrated that careful optimization of the HfO2 thickness and the Hf–Si composition can suppress both modes. As a result, a high electron mobility equivalent to that of n+polycrystalline silicon (poly-Si)/SiO2 (248 cm2 V-1 s-1 at Eeff=1 MV/cm) was obtained at Tinv of 1.47 nm. Moreover, the effective work function of the optimized Hf–Si/HfO2 gate stack is located within 50 mV from the Si band edge (Ec). An extremely high Ion of 1165 µA/µm (at Ioff = 81 nA/µm) at Vdd=1.0 V was demonstrated for a 45 nm gate n-channel metal–oxide–semiconductor field-effect transistor (n-MOSFET) without strain enhanced technology.