Tony Påhlsson

A 9-band WCDMA/EDGE transceiver supporting HSPA evolution

The future of cellular radio ICs lies in the integration of an ever-increasing number of bands and channel bandwidths. Figure 21.2.1 shows the block diagram of our transceiver, together with the associated discrete front-end components. The transceiver supports 4 EDGE bands and 9 WCDMA bands (I-VI and VIII-X), while the radio can be configured to simultaneously support the 4 EDGE bands and up to 5 WCDMA bands: 3 high bands (HB) and 2 low bands (LB). The RX is a SAW-less homodyne composed of a main RX and a diversity RX. To reduce package complexity with so many bands, we chose to minimize the number of ports by using single-ended RF interfaces for both RX and TX. This saves several package pins, but requires careful attention to grounding. The main RX has 8 LNA ports and the diversity RX has 5, with some LNAs supporting multiple bands. On the TX side, 2 ports are used for all EDGE bands and 4 for the WCDMA bands.

A 16–20 GHz LO system with 115 fs jitter for 24–30 GHz 5G in 28 nm FD-SOI CMOS

A system for mmW LO signal generation targeting 5G is presented. The proposed concept achieves high LO spectral purity at mmW frequencies using standard CMOS SOI technology. The measured performance is in line with 5G outdoor system requirements, which due to multi-path propagation require a smaller sub-carrier spacing than recent indoor mmW systems like IEEE 802.11ad. A set of two fractional-N, PLL based frequency synthesizer instances of the scalable LO system proposed has been implemented in 28 nm FD-SOI CMOS technology, where the chip area of one instance is only 0.11 mm2. Each PLL achieves an in-band phase noise below −100 dBc/Hz for a 28 GHz carrier while consuming just 15 mW from a 1.2 V supply. The FoMj is −244 dB which is the best reported figure for a fractional-N PLL in this frequency range.