Andreas Axholt

A PLL based 12GHz LO generator with digital phase control in 90nm CMOS

A 12 GHz PLL with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. Locally placed PLLs eliminate the need of long high frequency LO routing to each transceiver in a phased array circuit. Routing losses are thereby reduced and design of integrated phased array transceivers become more modular. A chip was manufactured, featuring two separate fully integrated PLLs operating at 12 GHz, with a common 1.5 GHz reference. The chip, including pads, measures 1050 × 700 ¿m2. Each PLL consumes 15 mA from a 1.2 V supply, with a typical measured phase noise of -110 dBc/Hz at 1 MHz offset. The phase control range exceeds 360°.

A 0.25W fully integrated class-D audio power amplifier in 0.35μm CMOS

A fully integrated class-D audio power amplifier using Pulse Width Modulation (PWM) technique is presented. The output stage is an H-bridge with 5.75 mm wide nMOS transistors and 15 mm wide pMOS transistors, which can deliver up to 0.25 Wrms to an 16 Omega load. The chip measuring 1.2times2.4 mm2, including pads, was fabricated in a 0.35 mum CMOS process. It uses a single 3.3 V supply and a PWM carrier frequency of 2.5 MHz. The chip was designed and simulated with Cadence IC design tools as a student project in the course IC- project and verification at Lund University. The chip was verified and works well with a measured THD+N of 0.5% and efficiency of 76% at 0.25 Wrms output power into 16 Omega.

Teaching top down design of analog/mixed signal ICs through design projects

This paper describes a project course that focuses on the design of analog and mixed signal circuits through a systematic top down design flow. In the project, the student will be involved in the planning, modeling, circuit level design, physical level implementation and measurement verification of for example a successive approximation (SA) ADC or a class-D audio amplifier. Throughout the project, the project members will improve their design skills and create an understanding for the importance of a systematic top-down design methodology at the different levels of the design flow.

A 24-GHz 90-nm CMOS beamforming receiver front-end with analog baseband phase rotation

A 24 GHz 2-path beamforming receiver front-end in 90 nm CMOS is presented. It consists of two direct conversion front-ends followed by a baseband block performing phase rotation and signal combination. The baseband phase rotation is performed by combining the quadrature phases using digitally controlled weights, achieving a phase resolution of 11 degrees. From each of the two inputs the front-end measures; a conversion gain of 13 dB, NF < 9 dB, ICP<inf>1db</inf> = −20.5dBm, IIP3 = −7.5dBm, LO-RF isolation 48dB, all at a power consumption of 33.6mW from a 1.2 V supply. The chip area is 1400}850 µm², including pads, of which the phase rotation block occupies 400}100 µm².

An Integrated 3-Level Fully Adjustable PWM Class-D Audio Amplifier in 0.35μm CMOS

A class-D audio amplifier utilizing a fully adjustable 3-level pulse width modulation (PWM) is presented. The amplifier is fully integrated in a 0.35 μm CMOS process, and is powered by a 3.3 V power supply. The system includes an internal fully adjustable triangle-wave oscillator, which is used to generate the PWM carrier. Delivering an output power of 300 mW is a differential bridge (7.5 cm pMOS, 3 cm nMOS), driving a 16 Ω load. The THD+N of the system is less than 0.2%, and the efficiency at 300 mW is 89%.

A 2.25mW inductor-less 24 GHz CML frequency divider in 90nm CMOS

A wideband low power CML frequency divider suitable for the Ku band has been designed and fabricated in a 90nm CMOS technology. Simulated phase noise and sensitivity curves are validated through on-wafer probe measurements. The maximum operating frequency is 24 GHz while dissipating 2.25 mW from a 1.5 V supply, resulting in a power-delay product of just 11.7 fJ. The divider measures 34 µm × 42 µm, including AC coupling capacitors. It was measured using an on chip 24 GHz differential LC VCO for input signal generation.

A 90 nm CMOS 14.5 GHz Injection Locked LO generator with digital phase control

A 14.5 GHz Injection Locked Oscillator (ILO) with digital output phase control has been implemented in a 90 nm CMOS process. It is intended for LO signal generation in integrated phased array transceivers. The chip, measuring 360×530 µm2 including pads, was characterized using on-wafer probing. It has a 1.4 GHz frequency range where full 3600 phase range is achieved with 3rd order subharmonic mixers. The free running phase noise is −105 dBc/Hz at 1 MHz offset. It consumes 9.4 mA from a 1.2 V supply.

A 90nm CMOS UWB LNA

A single-ended two=stage 3.1-10.6 GHz Low Noise Amplifier aimed for Ultra Wide Band (UWB) communication is presented. The LNA is fabricated in a 90 nm CMOS process and measures just 0.31×0.41 mm2 including pads. The first stage topology is common-gate, to achieve a wideband input match. The second stage is a common source stage with resistive shunt feedback, to achieve high and flat gain over a wide frequency range. The chip was measured using RF-probes and has a gain of 17.25±1.25 dB, a noise figure of 4.1=9.4 dB, and an input reflection S11 better than -12 dB between 3.1 GHz and 10.6 GHz, while consuming 8.6 mA from a 1V supply.