Jannik Hammel Nielsen

A distributed transducer system for functional electrical stimulation

Implanted transducers for functional electrical stimulation (FES) powered by inductive links are subject to conflicting requirements arising from low link efficiency, a low power budget and the need for protection of the weak signals against strong RF electromagnetic fields. We propose a solution to these problems by partitioning the RF transceiver and sensor/actuator functions onto separate integrated circuits. By amplifying measured neural signals directly at the measurements site and converting them into the digital domain before passing them to the transceiver the signal integrity is less likely to be affected by the inductive link. Neural stimulators are affected to a lesser degree, but still benefit from the partitioning. As a test case, we have designed a transceiver and a sensor chip which implement this partitioning policy. The transceiver is designed to operate in the 6.78 MHz ISM band and consumes approximately 360 /spl mu/W. Both chips were implemented in a standard 0.5 /spl mu/m CMOS technology, and use a 3 V supply voltage.

An Implantable CMOS Amplifier for Nerve Signals

AbstractIn this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 10 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 4.8 nV/

A low-power CMOS front-end for cuff-recorded nerve signals

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An implantable CMOS amplifier for nerve signals

. The amplifier power consumption is 275 μW, drawn from a power supply; VDD = −VSS = 1.5 V.

Technology scaling impact on embedded ADC design for telecom receivers

A 10bit SAR-ADC implemented in a 1.2V 0.13mum CMOS with 1VppdiffFS, based on capacitive-charge redistribution can be programmed with Fs up-to-6MS/s, guaranteeing an ENOB>9b with a SFDR>74dB. The static INL and DNL are 0.6LSB and 0.55LSB, respectively. On-chip reference buffer have been added and their power consumption dominates, giving a FoMap1pJ/conv. Sharing these buffers with other blocks in SoC structure, reduces the ADC power consumption to 200muW and the FoMap0.1pJ/conv. This appears an attractive solution for embedded ADC

A low-power 10-bit continuous-time CMOS /spl Sigma//spl Delta/ A/D converter

A low-power signal sensor front-end for biomedical applications is presented. The front-end consists of a preamplifier and an AID converter (ADC) for quantizing the sensor readout signal. The amplifier achieves low thermal noise by utilizing the weak inversion biasing region of MOSTs and low I/f-noise by chopper modulation. The resulting equivalent input referred noise is 7 nV/Hz, for a chopping frequency of 20 kHz. The implemented gain is 72.5 dB over a signal bandwidth of 4 kHz. The ADC is implemented as a third order ΣΔ-modulator employing a continuous-time (CT) loop filter. The loop filter integrators are implemented as Gm - C elements. The ADC signal-to-noise- and-distortion-ratio (SNDR) is measured to 62 dB, equivalent to 10 bits performance over a 4 kHz bandwidth and a dynamic range (OR) of 67 dB. The systems draws 353 μW of power from a modest supply voltage of 1.8 V.

Implantable CMOS front-end for nerve-signal sensors

In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) /spl Sigma//spl Delta/ A/D converters. A method for performance prediction for /spl Sigma//spl Delta/ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power efficient configuration of a CT single-loop /spl Sigma//spl Delta/ ADC. Finally, a 10 bit prototype converter is optimized and simulated using a 0.35 /spl mu/m CMOS technology. The simulation results of the prototype 1.8 V converter show a SNR better than 65 dB and a spurious-free dynamic range of more than 63dB, consistent with 10 bits performance. Expected power consumption for the prototype is approx. 170 /spl mu/W.

Impact of oscillator power in discrete and continuous time /spl Sigma//spl Delta/ converters

In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 /spl mu/m CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 5 nV//spl radic/Hz. The amplifier power consumption is 275 /spl mu/W.