Toru Kaga

A fully depleted lean-channel transistor (DELTA)-a novel vertical ultrathin SOI MOSFET

A fully depleted lean-channel transistor (DELTA) that has a gate with a vertical ultrathin SOI structure is reported. In the deep submicrometer region, selective oxidation is useful in realizing SOI isolation. It provides high crystalline quality, as good as that of conventional bulk single-crystal devices. Using experiments and three-dimensional simulation, it was shown that the gate structure has effective channel controllability and its vertical ultrathin SOI structure provides superior device characteristics.<<ETX>>

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 mu m/sup 2/ crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 mu m electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs. >

A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET

A fully depleted lean channel transistor (DELTA) having a gate structure and vertical ultrathin SOI (silicon-on-insulator) structure with selective field oxide is reported. In the deep submicron region, selective oxidation is useful for achieving SOI isolation. It provides a high-quality crystal and a Si-SiO/sub 2/ interface as good as those of conventional bulk single-crystal devices. Using experiments and simulation, it was shown that the gate structure of DELTA has effective channel controllability and its vertical ultrathin (<0.2- mu m) SOI structure provides superior device characteristics, e.g. the reduction of short channel effects, minimized subthreshold swing, and high transconductance. The DELTA layout is consistent with the conventional ULSI circuit layout. Thus, DELTA offers both consistency with conventional MOSFETs and good scalability As a 3-D device. As a result, DELTA provides a promising approach for MOSFET structures of less than 0.1 mu m in size.<<ETX>>

Impact of the vertical SOI 'DELTA' structure on planar device technology

A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultrathin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control and that the vertical ultrathin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance. >

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3- mu m electron-beam lithography. This memory cell has an area of 1.28 mu m/sup 2/. The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 mu m, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 mu m/sup 2/ because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta/sub 2/O/sub 5/ film equivalent to a 2.8-nm SiO/sub 2/ film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation. >

Crystallization‐induced stress in silicon thin films

Residual stress change in silicon thin films during crystallization of amorphous silicon is discussed experimentally by detecting the wafer curvature change using a scanning laser microscope. The as‐deposited amorphous‐silicon film shows compressive stress of about 200 MPa. During a crystallization reaction at about 650 °C, a large tensile stress of about 1000 MPa develops in the film due to film shrinkage. The final residual stress of polycrystalline film depends on the film formation process.

A new stacked cell structure for giga-bit DRAMs using vertical ultra-thin SOI (DELTA) MOSFETs

Summary form only given. The first stacked DRAM (dynamic RAM) cell using vertical ultra-thin SOI (silicon-on-insulator) MOSFET (DELTA, or fully depleted lean-channel transistor) is proposed. Since the ultra-thin SOI structure provides high noise immunity, the storage node capacitance can be reduced by more than 50%. Therefore, in the proposed DRAM cell a large storage capacitor need not be essential, and this will extend the DRAMs miniaturization to the gigabit levels. The cell structure schematic is shown and threshold voltage dependences on channel length of DELTA-, conventional NMOS-, and PMOS-FETs are demonstrated. DELTA shows good short channel characteristics compared to conventional NMOS.<<ETX>>

Short- and long-term reliability of nitrided oxide MISFETs

The short- and long-term reliability of thin nitrided oxide (oxynitride) films is studied. Tests conducted on several oxynitride films fabricated under various nitridation conditions show that (1) the defect density of thin (5-nm) oxynitride film is very low; (2) oxynitride MISFETs exhibit less transconductance degradation due to hot-carrier injection than oxide MISFETs; (3) these thin films have superior time-dependent dielectric breakdown characteristics; and (4) the electron traps in oxynitride film are drastically reduced by annealing in an O/sub 2/ gas atmosphere. >

Process and device technologies for 1 Gbit dynamic random‐access memory cells

This article discusses the technological issues involved with continuing the miniaturization of dynamic random‐access memory cells into the gigabit era. Ever‐smaller giga‐generation dynamic random‐access memory cells require three‐dimensional high‐charge density capacitors with high‐e insulating films, leading to the need for further improvements in lithographic resolution for ever‐smaller, higher aspect ratio memory cells, and planarization technologies for reducing the memory‐cell height. This article demonstrates two technologies for meeting these two requirements: high acceleration energy electron‐beam lithography and KrF excimer‐laser phase‐shift photolithography, and plate‐wiring merge technology. Metal–insulator–metal 1.6 nm Ta2O5 CROWN capacitors and single Si3N4 spacer OSELO isolation technology for an experimental 1 Gbit dynamic random‐access memory chip are also discussed.

A Block-oriented Ram With Half-sized Dram Cell And Quasi-folded Data-line Architecture

The authors describe a block-oriented random-access memory (BORAM) based on a series-connected cell concept and a quasi-folded data-line architecture. The series-connected cell concept allows a nearly half-sized DRAM cell even when using the same fabrication process as for conventional DRAMs. The low-noise quasi-folded data-line architecture allows the data-line capacitance to be one eighth the conventional value at the minimum, or the number of cells per amplifier to be 64 times the conventional number at the maximum. In addition, this architecture provides a more relaxed layout for the READ/WRITE circuits. The operation of four series-connected cells is observed successfully through a test device which includes a voltage-to-current conversion circuit, a current-mirror amplifier, and a 0.76- mu m/sup 2/ crown-shaped stack-capacitor (STC) cell. >