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Dive into the research topics where Toru Shonai is active.

Publication


Featured researches published by Toru Shonai.


integrated network management | 2003

VPDC: virtual private data center: a flexible and rapid workload-management system

Mineyoshi Masuda; Yutaka Yoshimura; Toshiaki Tarui; Toru Shonai; Mamoru Sugie

Rapid server allocation implemented on a virtual private data center (VPDC), which is an autonomous server allocation system for a three-tier Web system, has been developed and tested. The test results show that, with this new system, elapsed time for application server allocation is about 20 seconds, and that for database server allocation is within 140 seconds.


Archive | 2002

Computer resource allocating method

Yutaka Yoshimura; Toshiaki Tarui; Frederico Buchholz Maciel; Toru Shonai


Archive | 2001

Apparatus and method for dynamically allocating computer resources based on service contract with user

Yoshiko Tamaki; Toru Shonai; Nobutoshi Sagawa; Shun Kawabe


Archive | 2002

DEVICE AND METHOD FOR DIVIDING COMPUTER RESOURCES

Takashi Kawabe; Nobutoshi Sagawa; Toru Shonai; Yoshiko Tamaoki; 暢俊 佐川; 亨 庄内; 峻 河辺; 由子 玉置


Archive | 2000

Node controller for performing cache coherence control and memory-shared multiprocessor system

Tsuyoshi Tanaka; Hideya Akashi; Yuji Tsushima; Keitaro Uehara; Naoki Hamanaka; Toru Shonai


Archive | 2001

Computer forming logical partitions

Toshiaki Tarui; Shin Kameyama; Frederico Buchholz Maciel; Toru Shonai


Archive | 1998

Shared memory multiprocessor performing cache coherency

Toshiaki Tarui; Koichi Okazawa; Yasuyuki Okada; Toru Shonai; Toshio Okochi; Hideya Akashi


Archive | 2003

Shared memory multiprocessor performing cache coherence control and node controller therefor

Yoshiko Yasuda; Naoki Hamanaka; Toru Shonai; Hideya Akashi; Yuji Tsushima; Keitaro Uehara


Archive | 1993

Automatic logic designing method and system

Naohiro Kageyama; Toru Shonai; Rikako Suzuki; Takashi Okada; Kazuhiko Iijima; Hiroyuki Nakajima; Chihei Miura; Tsuguo Shimizu


Archive | 1999

Cache memory control circuit including summarized cache tag memory summarizing cache tag information in parallel processor system

Hideya Akashi; Toshio Okochi; Toru Shonai; Masamori Kashiyama

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