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Featured researches published by Tetsuhiko Okada.


Proceedings of COMPCON '94 | 1994

A PA-RISC microprocessor PA/50L for low-cost systems

Tetsuhiko Okada; Susumu Narita; Osamu Nishii; Noriharu Hiratsuka; Nobuyuki Hayashi; Mitsuo Asai; Shinji Fujiwara; Mikiko Satoh; Junichi Nishimoto; Hirokazu Aoki; Kunio Uchiyama; Shigeru Matsuo; Hidehito Takewa; Kouji Yamada; Masahiro Kainaga; Norio Nakagawa; Masanobu Yamagami; Hiroshi Takeda; Tsuneo Funabashi

The PA/50L is a low-cost, low-power microprocessor from Hitachi Ltd. that is fully compatible with the PA-RISC architecture 1.1, third edition. This microprocessor achieves 55 VAX MIPS (Dhrystone 1.1), 10.6 MFLOPS (LINPACK inner loop) and 1.3 W at 33 MHz. In order to achieve high performance with no external cache, a non-blocking cache and a data prefetch instruction are provided. This paper gives an overview of the microprocessor and describes its capabilities.<<ETX>>


Archive | 1995

Method for prefetching pointer-type data structure and information processing apparatus therefor

Tetsuhiko Okada; Osamu Nishii; Hiroshi Takeda


Archive | 1996

Multi-processor system and its network

Tetsuhiko Okada; Naoki Hamanaka; Naohiko Irie; Takehisa Hayashi; Tetsuya Mochida; Masabumi Shibata; Youichi Tanaka; Yasuhiro Ishii


Archive | 1993

Microprocessor capable of decoding two instructions in parallel

Susumu Narita; Fumio Arakawa; Tetsuhiko Okada; Kunio Uchiyama


Archive | 1995

Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment

Nobukazu Kondo; Seiji Kaneko; Hideaki Gemma; Tetsuhiko Okada; Kazuhiko Komori; Koichi Okazawa


Archive | 1990

PIPELINE PROCESSOR WITH PREFETCH CIRCUIT

Susumu Narita; Makoto Hanawa; Tadahiko Nishimukai; Tetsuhiko Okada


Archive | 2000

Multiprocessor system and methods for transmitting memory access transactions for the same

Yuji Tsushima; Hideya Akashi; Keitaro Uehara; Naoki Hamanaka; Toru Shonai; Tetsuhiko Okada; Masamori Kashiyama


Archive | 1994

Input/output control method and data processor

Tetsuhiko Okada; Hideki Murayama; Takehisa Hayashi; Atsushi Ugajin; Yasuhiro Ishii; Masahiro Kitano


Archive | 1993

Network adaptor device

Takeshi Aimoto; Hidenori Inai; Shoichi Murase; Hideki Murayama; Tetsuhiko Okada; 秀則 井内; 哲彦 岡田; 秀樹 村山; 彰一 村瀬; 毅 相本


Archive | 2000

Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer

Hideya Akashi; Yuji Tsushima; Keitaro Uehara; Naoki Hamanaka; Toru Shonai; Tetsuhiko Okada; Masamori Kashiyama

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