Toshifumi Nakatani

A wide dynamic range switched-LNA in SiGe BiCMOS

A wide dynamic range, high current efficient switched-LNA has been developed by using SiGe BiCMOS technology. The low loss RF MOSFET reduced silicon substrate effect at high frequency is used as a bypass switch for the LNA. The 800-900 MHz LNA is demonstrated in this work. In high gain/low distortion mode for transmitting and receiving simultaneously, the amplifier achieves 15.3 dB gain, 1.4 dB noise figure and +1.6 dBm IIP3 with 5.9 mA DC current. In high gain/low current mode for receiving only, 13.3 dB gain, 1.6 dB noise figure and -0.6 dBm IIP3 are achieved with 3.0 mA. In low gain mode, 1.5 dB insertion loss and +16.1 dBm IIP3 with <10 /spl mu/A are realized by the bypass switch. The switched-LNA is housed in a very small and low cost SON12 plastic package with a down-mixer.

Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications

A digitally-controlled polar transmitter with a watt-class CMOS power amplifier is demonstrated, implemented in a 0.15 μm RF CMOS process. Stacked FETs in a current-mode class-D configuration are used to obtain high breakdown voltage and high efficiency in the output stage, and a doughnut-shaped Guanella reverse balun is applied to achieve a 1-to-4 impedance transformation with less than 1 dB insertion loss. The amplifier has 31 dBm output power with 51% drain efficiency at 0.75 GHz frequency under single tone testing. The output stage is fed by a buck converter employing digital pulsewidth modulation with 47 MHz pulse rate synchronized with a 3 GHz clock. Digital compensation techniques were developed to maintain linearity. WCDMA HPSK modulation was demonstrated using a pulse pattern generator-based measurement bench. Overall efficiency of 26.5% was achieved while maintaining ACLRs within 3GPP specifications at 24 dBm average output power.

Digital polar transmitter using a watt-class current-mode class-D CMOS power amplifier

A digital polar transmitter with a watt-class CMOS power amplifier is demonstrated, implemented with a 0.15um RF CMOS process. Current-mode class-D configuration and stacked FETs are used to obtain high efficiency and high breakdown voltage in the output stage, which was measured to have 31 dBm output power with 51% drain efficiency under single tone testing. The output stage is fed by a buck converter employing digital pulse width modulation with 47 MHz pulse rate synchronized with a 3 GHz clock. Digital compensation techniques were developed to maintain linearity. WCDMA HPSK modulation was demonstrated using a pulse pattern generator-based measurement bench. Overall efficiency of 26.5 % efficiency was achieved while maintaining ACLRs within 3GPP specifications at 24 dBm average output power.

Signal generation algorithm for digital polar transmitters with reduced receive band noise

Digital polar transmitters are under development for multiband handset applications, but typically lead to excess Rx band noise (RxBN). In this paper, a technique to improve the RxBN of a digital polar transmitter is demonstrated. Linear phase FIR filters are applied to both envelope and phase signals, so that the RxBN becomes relatively insensitive to transmitter non-idealities. At the same time, there is only small degradation of ACLR and EVM. Noise shaping algorithms are also applied to reduce the envelope quantization noise. For a WCDMA signal at 1.75 GHz, with a corresponding Rx band at 1.845 GHz, we demonstrate RxBN of -142 dBm/Hz in simulation and -125 dBm/Hz in experimental measurements.

Multiband and Wide Dynamic Range Digital Polar Transmitter Using Current-Mode Class-D CMOS Power Amplifier

Techniques are demonstrated to extend the power control dynamic range of a digitally-driven 0.15 um CMOS polar power amplifier to the degree needed for WCDMA handset applications. The output frequency can be tuned over the 0.75-2GHz range, using an on-chip band-switching resonator, and output power of 27-29 dBm is attained. By partitioning the switching PA into multiple 3-state unit cells, power dynamic ranges of 91 / 85 dB are achieved at 0.85 / 1.75 GHz while maintaining high efficiency. By introducing a buck converter that can act not only with pulse width modulation but also in charge sampling mode, the overall DC power consumption in the power back- off regime can be reduced by a factor of approximately 0.7.

A simple method for measuring the IM3 components of multi-stage cascaded power amplifiers considering the phase characteristics

A simple method has been proposed for the measurement of the output power and phase characteristics of the IM3 components appearing in multi-stage power amplifiers. By adopting a unique definition of the phase for the IM3 components that is independent of the delay time caused by transmission line and other instrument devices, it is possible to measure the phase, merely by using a vector signal analyzer. It is demonstrated that an accurate estimation of the IM3 characteristics of a two-stage cascaded power amplifier for cellular radio handheld terminals can be made by using the IM3 characteristics of the 1st and 2nd-stage amplifiers measured by the proposed method.

A New Design Concept for Balanced-Type SAW Filters Using a Common-Mode Signal Suppression Circuit

A new design concept for a common-mode signal suppression circuit for a balanced-type filter has been investigated. The degradation mechanism of the balance characteristics was studied. The degradation is caused by the common-mode signals combined with the differential-mode signals in the balanced terminals. The concept employed is the reduction of the common-mode signal using a common-mode signal suppression circuit, connected to the balanced terminals. A serial resonance circuit is formed, in which the common-mode signals are shorted to ground. The circuit was applied to the balanced-type Surface Acoustic Wave (SAW) filter. The improvement in balance characteristics, without increasing in the insertion loss, was confirmed by experiments for Global System Mobile (GSM) applications.

A 1–3 GHz Delta–Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI

This paper presents a new fully digital architecture for an RF phase modulator with significantly improved phase resolution. The modulator utilizes 32 variable delay-lines in a delay-locked loop (DLL) configuration to provide 1–3 GHz operation with coarse 5-bit resolution. A 5-bit low-glitch multiplexer with accurate delay control on the control lines is used to select different taps of the DLL according to the baseband digital phase data to generate the desired phase modulated signal at the output. To further increase the effective resolution, a high speed 10-bit input, 5-bit output digital delta–sigma modulator (DSM) is added in front of the multiplexer. The DSM compensates for the phase truncation occurring in the 5-bit DLL. The impact of delay mismatch and phase offset in the DLL on the phase modulator output performance are studied. The phase modulator IC is implemented in 45-nm CMOS SOI and achieves <2% rms EVM together with 55-dB rejection of close-to-carrier emissions for an 8-Mb/s GMSK signal at 2.3 GHz, with power consumption below 35 mW.

A wideband delta-sigma based closed-loop fully digital phase modulator in 45nm CMOS SOI

This paper presents a new architecture for an RF phase modulator that significantly improves the phase resolution. The modulator utilizes 32 variable delay elements in a delay lock loop (DLL) configuration to provide wideband 1-3GHz operation with coarse 5-bit resolution. A 5-bit multiplexer selects different taps of the DLL according to the baseband digital phase data to generate desired phase modulated signal at the output. A high speed 5-bit digital delta-sigma modulator is additionally used to compensate for the phase truncation occurring in the 5-bit DLL. The phase modulator IC is implemented in 45nm CMOS SOI and achieves <;2% rms EVM while achieving 55dB rejection of close-to-carrier emissions for an 8Mb/s GMSK signal at 2.3GHz, with power consumption below 35mW.

Techniques for Power Dynamic Range and Back-Off Efficiency Improvement in CMOS Digitally Controlled Polar Transmitters

Techniques to extend the power dynamic range and to reduce the dc power consumption in back-off for a multiband CMOS digitally controlled polar transmitter are described. The techniques are applied to a transmitter comprising a digitally controlled buck converter and a current-mode class-D RF amplifier with digitally controlled unit cells. The power dynamic range is improved by using tri-state unit-cells (rather than the customary “on-off” controlled cells) to reduce the feed-through power. The measured overall power dynamic ranges are 91 and 85 dB, at 0.85 and 1.75 GHz, respectively. DC power consumption at low power was reduced by introducing a new charge-sampling mode of operation for the buck converter in addition to the customary pulse-width modulation operation. Experimental results showed dc power consumption reduced by 30% at low power.