Toshifumi Yamaji

Influence of the Existence of an Underlying SiO2 Layer on the Lateral Solid‐Phase Epitaxy of Amorphous Silicon

The influence of the existence of an underlying SiO 2 layer on the lateral solid-phase epitaxy (L-SPE) of amorphous Si was investigated by comparing the characteristics of L-SPE with and without an underlying SiO 2 layer. For the L-SPE with an underlying SiO 2 layer which had a change from {110} to {111} facet growth, high density crystal defects, most of which were dislocations, were detected especially in the {111} facet growth region. The formation of {111} facets is caused primarily by high density dislocations incorporated by relaxation of the stress which originates from the retardation of Si atom rearrangement

Optimization of low-temperature poly-Si TFT-LCDs and a large-scale production line for large glass substrates

An update of the progress of inherently low-temperature poly-Si (LTPS) technologies, such as ELA, ion doping, and activation in conjunction with chemical vapor deposition (CVD) and pho. tolithography will be given. We will also discuss whether LTPS LCDs will be applied to a large-scale production line using a large motherglass substrate. It was found that a more-powerful excimer laser as well as photolithography with higher-resolution and a more-precise overlaid arrangement woulc enable a large-scale production line handling motherglass of 4th generation size to be constructed ir the very near future with reasonable investment and productivity costs.

A Novel Fabrication Technique of Multilayer Stacked Silicon-on-Insulator Structure Applicable to Three-Dimensional ICs

In this study, in order to investigate the feasibility of three-dimensional ICs fabricated using the combined techniques of lateral-solid phase epitaxy (L-SPE) and selective epitaxial growth (SEG) of Si, we fabricated a 5-layer stacked SOI structure and studied its characteristics. In this procedure, both epitaxy of Si for SEG on seeded windows and deposition of amorphous-Si for L-SPE were performed using ultra-low-pressure chemical vapor deposition. As a result, all single-crystalline SOI regions on each stacked layer exhibit the same graded crystallinity. We also fabricated n-channel metal oxide semiconductor field effect transistors onto the top layer. A maximum µFE of 617 cm2/(Vs) was obtained. This is the first report on the single-crystalline 5-layer stacked SOI structure.