Toshikazu Sei

A high-speed low-power 0.3 /spl mu/m CMOS gate array with variable threshold voltage (VT) scheme

Circuit techniques for dynamically varying threshold voltage are introduced to reduce active power dissipation by 50% with negligible overhead in speed, standby power and chip area. No additional external power supply or additional step in process is required. A gate array with this scheme is fabricated in a 0.3 /spl mu/m CMOS technology whose performance is investigated. The gate array is best fit for multimedia portable applications that require low standby power dissipation and high performance.

A 0.5 mu m BiCMOS SOG with selectable 5 V/3.3 V operations

A 0.5- mu m BiCMOS SOG (sea-of-gates) with selectable 5-V/3.3-V operations is described. On-chip voltage converters for power distribution and selectable 5-V/3.3-V level interface circuits are proposed and successfully applied to a BiCMOS SOG with an optimized array architecture. High-speed, low-power, and high-reliability operations are demonstrated with a 0.5- mu m BiCMOS process and 3.3-V operation.<<ETX>>