Yukinori Uchino

Built-in self-repair circuit for high-density ASMIC

A built-in self-repair (BISR) circuit is introduced to achieve high yield and to overcome the testing problem for high-density application-specific memory ICs (ASMIC). The feasibility of BISR is demonstrated for a 1-Mb DRAM embedded gate array. A die-sort strategy using BISR is also discussed

A 72 K CMOS channellers gate array with embedded 1 Mbit dynamic RAM

A 1-Mb DRAM (dynamic random-access memory) is embedded in a 72-K-raw-gates channelless gate array fabricated in 1.0- mu m HC/sup 2/MOS twin-well technology. The DRAM design is optimized for embedding, such as the adaptation of no substrated bias design and p-well protected n-channel memory cells. The typical delay time of the gate array is 0.4 ns, and the worst-case access time of the DRAM is 60 ns.<<ETX>>