Toshiki Shinmura

Cu/poly-Si damascene gate structured MOSFET with Ta and TaN stacked barrier

A Cu/Si layered-gate-structured MOSFET with Ta and TaN stacked barrier layers fabricated using a Cu damascene process has been developed for high-performance and reliable Si ULSI devices. A sheet resistance of 0.5 ohm/sq. was achieved with a 0.25 /spl mu/m gate length. The Ta and TaN layers guarantee reliable gate oxide (7.5 nm) after 500/spl deg/C thermal processing in nitrogen with forming gas annealing.

Practical Monte Carlo sputter deposition simulation with quasi-axis-symmetrical (QAS) approximation

A practical Monte Carlo (MC) sputter deposition profile model has been developed to achieve accurate profile simulation within reasonable calculation time. The key features of the model are: (1) a quasi-axi-symmetrical (QAS) approximation which enables to convert 3D trajectories of incident atoms into 2D sputter deposition profiles in terms of the string model, and (2) calculation of the collision cross-section by means of Lennard-Jones potential. The simulated profiles of collimated-sputter titanium (Ti) in contact holes well agree with the experimental SEM profiles within 5% accuracy.<<ETX>>

A sputter equipment simulation system including molecular dynamical target atom scattering model

We have developed an advanced sputter equipment simulation system to design the deposition equipment for ULSI with high aspect ratios contact holes. The system is composed of a newly developed target atom scattering model and die profile model with the Monte Carlo (MC) method. The target atom scattering model uses the Molecular Dynamics (MD) technique combined with thermal analysis and derives ejection angle distribution. The simulated results of titanium (Ti) bottom coverage vs. applied voltage agree with experiments within 10% accuracy.