Toshiro Tsukada

Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits

This paper describes measurement of substrate noise waveforms in mixed-signal integrated circuits. This method uses wide-band chopper-type single-ended voltage comparators as on-chip noise detectors. By analyzing equivalently sampled comparator outputs in synchronized operation, the noise voltage in the auto-zero and compare modes can be measured separately, and noise waveforms were experimentally reconstructed to within 0.5-ns accuracy. The noise transmission path was analyzed, and this showed that the noise sampled at the auto-zero mode of the comparator can be used to reconstruct substrate noise waveforms with high resolution. The results also explain the influence of noise coupling on analog circuits widely used in on-chip analog-to-digital converters.

Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias

We propose a method of reducing substrate noise and random fluctuations utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip that contained 10-M transistors for measuring random fluctuation tendencies. Under SA-FBB conditions, it reduced noise by 69.8% and reduced random fluctuations /spl sigma/(I/sub ds/) by 57.9%.

On-chip active guard band filters to suppress substrate-coupling noise in analog and digital mixed-signal integrated circuits

An AC coupling configuration of active guard band filters can supply a substrate-coupling-noise cancellation signal to a ground-level substrate by using a single 3 V supply to on-chip circuits. Noise was suppressed to a maximum of less than 0.05 from 100 Hz to 2 MHz in a 0.35 /spl mu/m CMOS test chip. Experiments and a simulation based on the substrate model showed that the noise-suppression effect depends on the guard-band arrangement. The simulation is thus effective for optimizing the arrangement to strongly suppress noise effects.

A fast and accurate method of redesigning analog subcircuits for technology scaling

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to an MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods.

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond

Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset can-celing comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-μA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.

A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 h, making this method 5 times more efficient than conventional methods.

A 10b 3MSample/s CMOS cyclic ADC

This low-power, small-area, 10 b 3 MSample/s (0.33 /spl mu/s) CMOS on-chip ADC uses an improved recursive subranging approach. A multi-path cyclic-conversion architecture, an implementation of a recursive subranging architecture, is proposed to further reduce the power by reducing the required circuit speed. As a result, this ADC achieves compatibility between the low-power and small-area requirements. For on-chip system application, a module that includes bus interface circuitry and buffer amplifiers for the reference-voltage generators is implemented in addition to the 10 b 3 MSample/s ADC.

A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm

We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass ΔΣAD modulator to evaluate our new algorithms and architecture. We propose a new structure of a complex bandpass filter in the forward path with I, Q dynamic matching, that is equivalent to the conventional one but can be divided into two separate parts. As a result, the AS modulator, which employs our proposed complex filter can also be divided into two separate parts, and there are no signal lines crossing between the upper and lower paths formed by complex filters and feedback DACs. Therefore, the layout design of the modulator can be simplified. The two sets of signal paths and circuits in the modulator are changed between I and Q while CLK is changed between high and low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain period of time, and they are switched by multiplexers to those used for Q and I paths at another period of time. In this manner, the effect of mismatches between I and Q paths is reduced. Two nine-level quantizers and four DACs are used in the modulator for low-power implementations and higher signal-to-noise-and-distortion (SNDR), but the nonlinearities of DACs are not noise-shaped and the SNDR of the ΔΣAD modulator degrades. We have also employed a new complex bandpass data-weighted averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized by just adding simple digital circuitry. To evaluate these algorithms and architecture, we have implemented a modulator using 0.18 μm CMOS technology for operation at 2.8 V power supply; it achieves a measured peak SNDR of 64.5 dB at 20MS/s with a signal bandwidth of 78 kHz while dissipating 28.4 mW and occupying a chip area of 1.82 mm 2 . These experimental results demonstrate the effectiveness of the above two algorithms, and the algorithms may be extended to other complex bandpass ΔΣAD modulators for application to low-IF receivers in wireless communication systems.

Substrate noise measurement by using noise-selective voltage comparators in analog and digital mixed-signal integrated circuits

In mixed-signal ICs, substrate noise produced by high-speed digital circuits passes to the on-chip analog circuits through the substrate and seriously affects their performance. In this paper, we discuss how the substrate noise can be measured by using noise-selective chopper-type voltage comparators as noise detectors to detect the wide-band substrate noise so as to analyze and further reduce its effect. A switched capacitor is selectively loaded to the inverter amplifier of the comparator during the comparison period to reduce the noise detection at the transition from compare to auto-zero. The noise at the transition from auto-zero to compare can be selectively detected. Waveforms of the high frequency substrate noise were reconstructed by this on-chip noise detector incorporating the noise-selective comparators implemented using a 0.5-/spl mu/m CMOS bulk process.

An automatic error cancellation technique for higher accuracy A/D converters

An automatic error cancellation technique for higher accuracy successive-approximation analog/digital (A/D) converters is described. The technique uses a binary-weighted capacitor array as its own reference, and no other special elements are required for capacitor mismatch compensation. Experimental results indicate that more than 14-bit A/D conversion can be performed on a conventional MOS IC chip without trimming.