Satoshi Maeda

Oxidation rate reduction in the submicrometer LOCOS process

Experimental and analytical studies on submicrometer LOCOS oxide structures have been carried out. LOCOS oxide thickness reduction in submicrometer nitride windows has been newly observed. However, the birds beak length remains constant, in spite of decreasing the nitride window to 0.3 µm. In order to explain these results, a simple oxidation model is experimentally introduced that considers the lateral diffusion of oxidants from the nitride edge. Oxide thickness reduction is due to the decrease of oxidants in the submicrometer nitride window. A locus for the isolation region length in the etched back LOCOS process is also given by using our model. The nitride window sensitivity for LOCOS oxide structures should be considered during the process design for miniature devices with a submicrometer feature size.

Two-dimensional nature of diffused layers and certain limitations in scaling-down coplanar structure

Limitation of the coplanar technology to geometry miniaturization has been investigated. Two-dimensional nature of diffused line capacitance in a coplanar structure is investigated for the first time delineating importance of the sidewall capacitance with decreasing feature size of devices. The effects of field channel-stop ion implantation on the narrow-channel effect, the field MOS threshold voltage, and the junction breakdown voltage are also discussed.

Two dimensional nature of diffused line capacitance in coplanar MOS structures

Two dimensional nature of diffused line capacitance in the coplanar MOS LSI structure is investigated delineating importance of the side wall capacitance with decreasing feature size of devices. The effects of field channel stop ion implantation on the narrow channel effect, the field MOS threshold voltage and the junction breakdown voltage are also discussed toward optimization of coplanar process parameters.

Two-Dimensional Nature of Diffused Layers and Certain Limitations in Scaling-Down Coplanar Structure

Limitation of the coplanar technology to geometry miniaturization has been investigated. Two-dimensional nature of diffused line capacitance in a coplanar structure is investigated for the first time delineating importance of the sidewall capacitance with decreasing feature size of devices. The effects of field channel-stop ion implantation on the narrow-channel effect, the field MOS threshold voltage, and the junction breakdown voltage are also discussed.