Masahiko Hata

1-nm-capacitance-equivalent-thickness HfO2/Al2O3/InGaAs metal-oxide-semiconductor structure with low interface trap density and low gate leakage current density

We have studied the impact of the Al2O3 inter-layer on interface properties of HfO2/InGaAs metal-oxide-semiconductor (MOS) interfaces. We have found that the insertion of the ultrathin Al2O3 inter-layer (2 cycle: 0.2 nm) can effectively improve the HfO2/InGaAs interface properties. The frequency dispersion and the stretch-out of C-V characteristics are improved, and the interface trap density (Dit) value is significantly decreased by the 2 cycle Al2O3 inter-layer. Finally, we have demonstrated the 1-nm-thick capacitance equivalent thickness in the HfO2/Al2O3/InGaAs MOS capacitors with good interface properties and low gate leakage of 2.4 × 10−2 A/cm2.

Thin Body III--V-Semiconductor-on-Insulator Metal--Oxide--Semiconductor Field-Effect Transistors on Si Fabricated Using Direct Wafer Bonding

We have demonstrated thin body III–V-semiconductor-on-insulator (III-V-OI) n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) on a Si wafer fabricated using a novel direct wafer bonding (DWB) process. A 100-nm-thick InGaAs channel was successfully transferred by the low damage and low temperature DWB process using low energy electron cyclotron resonance (ECR) plasma. The transferred InGaAs-OI nMOSFET on the Si wafer exhibited a high electron channel mobility of 1200 cm2V-1s-1, indicating that the present DWB process allows us to form thin III-V-OI channels without serious plasma and bonding damage. This technology is expected to open up the possibility of integrating the ultrathin body III-V-OI MOSFETs on Si platform.

III-V-semiconductor-on-insulator n-channel metal-insulator-semiconductor field-effect transistors with buried Al2O3 layers and sulfur passivation: Reduction in carrier scattering at the bottom interface

We have developed III-V-semiconductor-on-insulator (III-V-OI) structures on Si wafers with excellent bottom interfaces between In0.53Ga0.47As-OI channel layers and atomic-layer-deposited Al2O3 (ALD-Al2O3) buried oxides (BOXs). A surface activated bonding process and the sulfur passivation pretreatment have realized the excellent In0.53Ga0.47As-OI/ALD-Al2O3 BOX bottom interface properties. As a result, the III-V-OI n-channel metal-insulator-semiconductor field-effect transistors under the back-gate configuration showed the peak mobility of 1800 cm2/V s and the higher electron mobility than the Si universal one even in the high effective electric field range because of the reduction in the surface roughness and fixed charges.

High Electron Mobility Metal–Insulator–Semiconductor Field-Effect Transistors Fabricated on (111)-Oriented InGaAs Channels

Metal–insulator–semiconductor field-effect transistors (MISFETs) were fabricated on the (111)A surface of In0.53Ga0.47As for the first time. Al2O3 gate dielectrics were formed by atomic layer deposition on sulfur-stabilized InGaAs surfaces. The MISFET on (111)A demonstrated channel mobility higher than that on (100), achieving more than 100% improvement with respect to Si even at a high surface carrier concentration.

Sub-10-nm Extremely Thin Body InGaAs-on-Insulator MOSFETs on Si Wafers With Ultrathin

We have demonstrated sub-10-nm extremely thin body (ETB) InGaAs-on-insulator (InGaAs-OI) nMOSFETs on Si wafers with Al₂O₃ ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding process. We have fabricated the ETB InGaAs-OI nMOSFETs with channel thicknesses of 9 and 3.5 nm. The 9-nm-thick ETB InGaAs-OI n MOSFETs with a doping concentration (N_D) of 10¹⁹ cm^-3 exhibit a peak electron mobility of 912 cm²/V·s and a mobility enhancement factor of 1.7 times against the Si nMOSFET at a surface carrier density (N_s) of 3 ×10¹² cm^-2. In addition, it has been found that, owing to Al₂O₃ UTBOX layers, the double-gate operation improves the cutoff properties. As a result, the highest on-current to the lowest off-current (I_on/I_off) ratio of approximately 10⁷ has been obtained in the 3.5-nm-thick ETB InGaAs-OI nMOSFETs. These results indicate that the high-mobility III-V nMOSFETs can be realized even in sub-10-nm-thick channels.

\hbox{Al}_{2}\hbox{O}_{3}

We report that a Ni–InGaAs alloy can be used as a source/drain (S/D) metal for InGaAs metal–oxide–semiconductor field-effect transistors (MOSFETs), allowing us to employ the salicide-like self-align S/D formation. We also introduce Schottky barrier height (SBH) engineering process by increasing the indium content of InxGa1-xAs channels, which successfully reduces SBH down to zero. We propose a fabrication process for self-aligned metal S/D MOSFETs using Ni–InGaAs and demonstrate successful operation of the metal S/D InxGa1-xAs MOSFETs. The In0.7Ga0.3As MOSFETs exhibit an S/D resistance (RSD) that is 1/5 lower than that in P–N junction devices and a high peak mobility of 2000 cm2 V-1 s-1.

Buried Oxide Layers

We have demonstrated extremely-thin-body (ETB) (3.5 and 9 nm) InGaAs-on-insulator (InGaAs-OI) MOSFETs on Si substrates with Al<inf>2</inf>O<inf>3</inf> ultrathin buried oxide (UTBOX) layers fabricated by direct wafer bonding (DWB). We have found that the ETB highly-doped InGaAs-OI n-channel MOSFETs without p-n junction can perform a normal MOSFET operation under front- and back-gate configuration and the double-gate operation can provide excellent on-current/off-current (I<inf>on</inf>/I<inf>off</inf>) properties of ∼10⁷ and the improved S factor even for InGaAs-OI MOSFETs with ND of 1×10¹⁹ cm⁻³.

Self-Aligned Metal Source/Drain InxGa1-xAs n-Metal–Oxide–Semiconductor Field-Effect Transistors Using Ni–InGaAs Alloy

Residual impurities in GaAs and AlGaAs grown using trimethylgallium (TMG), trimethylaluminum (TMA) and AsH3 were studied. The silicon compounds, the typical impurity in TMG/TMA, were considerably reduced by the refinement of the synthesis and purification processes. The epitaxial growth using the highly purified TMG (Si<0.2 ppm) showed that the purity of GaAs epitaxial layers was mainly affected by that of AsH3. In high purity layers (electron mobility at 77 K was 89,000–153,000 cm2/V·s). the main residual donors detected by photothermal ionization technique were germanium and silicon. Germanium was also detected by secondary ion mass spectroscopy in a less pure layer. Carbon acceptors were detected in all the layers through 4.2 K photoluminescence measurement. From these results, it was concluded that the purity of GaAs layers was determined by the donors, germanium and silicon, associated with AsH3 and the carbon acceptor from TMG. The influence of oxygen in source materials on the quality of AlGaAs layers was studied. The quality of the AlGaAs layers was found to be influenced by methoxide (-OCH3) in TMA and still more influenced by oxygen in arsine.

Extremely-thin-body InGaAs-on-insulator MOSFETs on Si fabricated by direct wafer bonding

We clarified that Fermi levels at InGaAs MOS interfaces are pinned inside conduction band (CB) and that this pinning severely degrades the effective mobility. Also, the energy position of the Fermi level pinning (FLP) is found to be tunable. It is experimentally shown that the increase in the difference between the FLP position and the CB minimum (CBM) leads to high mobility at high Ns region. Also, possible physical origin for this FLP is proposed.

Residual impurities in epitaxial layers grown by MOVPE

We have studied the impact of atomic-layer-deposition (ALD) temperature on the HfO2/InGaAs metal-oxide-semiconductor (MOS) interface with a comparison to the Al2O3/InGaAs interface. It is found that the interface properties such as the C-V characteristics and the interface trap density (Dit) and the interface structure of HfO2/InGaAs have strong dependence on the ALD temperature, while the Al2O3/InGaAs interfaces hardly depend on it. As a result, we have achieved the HfO2/InGaAs interfaces with low Dit comparable to that in the Al2O3/InGaAs interface by lowering the ALD temperature down to 200 °C or less. Also, we have found that As2O3 and Ga2O3 formed at the interface during ALD increase with a decrease in the ALD temperature. Combined with the ALD temperature dependence of the electrical characteristics, the better C-V characteristics and the lower Dit obtained at the lower ALD temperature can be explained by the As2O3 and Ga2O3 passivation of the HfO2/InGaAs interfaces, which is consistent with a repor...