Eiko Mieda

Demonstration of ultimate CMOS based on 3D stacked InGaAs-OI/SGOI wire channel MOSFETs with independent back gate

An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive back gate bias, VBG control.

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

High electron mobility triangular InGaAs-OI nMOSFETs with (111)B side surfaces formed by MOVPE growth on narrow fin structures

Triangular In_0.53Ga_0.47As-OI nMOSFETs with smooth (111)B side surfaces on Si have been successfully fabricated. Triangular shaped channels with bottom width down to 30 nm were formed by MOVPE growth on narrow InGaAs-OI fins. The formed (111)B surface was demonstrated to provide higher mobility compared with reference InGaAs-OI tri-gate (1.9×) as well as bulk (100) InGaAs nMOSFETs (1.6×), which is possibly due to reduced D_it in conduction band and resultant suppressed carrier trapping at the MOS interface. Lower noise and hysteresis in triangular device supported this model. High I_on value of 930 μA/μm at L_g = 300 nm indicates the potential of the triangular InGaAs-OI nMOSFETs for ultra-low power and high performance CMOS applications.

High mobility p-n junction-less InGaAs-OI tri-gate nMOSFETs with metal source/drain for ultra-low-power CMOS applications

We have successfully fabricated InGaAs-OI tri-gate nMOSFETs, for the first time. The devices were depletion-type (p-n junction-less) nFETs with Fin-channel width (W_fin) down to 20 nm and had metal source/drain structures. It was experimentally demonstrated that W_fin scaling effectively improved cut-off properties at N_d up to 5 × 10¹⁸ cm^-3 and the electron mobility in the narrowest channel (W_fin = 20 nm) was about 3x higher than that of the inversion layer. It was also demonstrated that enhancement of In content from 53% to 70% leaded to 30% I_on enhancement without I_off degradation.

Nanoprobe characterization of MoS2 nanosheets fabricated by Li-intercalation

We have fabricated MoS2 nanosheets by using a liquid-phase Li-intercalation method. To develop a process for the preparation of highly dispersed single-layer MoS2 nanosheets in water, we studied the mechanism of intercalation and exfoliation of MoS2. The water desorption behavior of the MoS2 nanosheets during heat treatment was investigated by in situ atomic force microscopy (AFM) and scanning transmission electron microscopy (STEM). By the analysis of each measurement, the amount of desorbed water existing in the interlayer and on the surface of MoS2 nanosheets could be estimated. Furthermore, we observed the water absorption behavior of Li-intercalated MoS2 by X-ray diffraction (XRD). From the results, we found that the layer distance was expanded to a thickness of more than two layers of water molecules intercalated by water absorption. These results are important to develop an effective approach to fabricate high-yield, single-layer MoS2 nanosheets dispersion based on a Li-intercalation method.

3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS

InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.

Suppression of short channel effects in accumulation-type UTB-InGaAs-OI nMISFETs with raised S/D fabricated by gate-last process

Accumulation-type (junction-less) 8-nm thick UTB-InGaAsOI nMISFETs with raised SD were fabricated by gate-last process. It was confirmed that the raised SD structure drastically reduced parasitic resistance at the SD regions. It was found that the short channel effects were comparable to those of gate-all-around FETs below Lg < 100 nm even with In content of 70%.