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Featured researches published by Toshiyuki Oishi.


IEEE Transactions on Electron Devices | 2013

AlGaN Channel HEMT With Extremely High Breakdown Voltage

Takuma Nanjo; Akifumi Imai; Yosuke Suzuki; Yuji Abe; Toshiyuki Oishi; Muneyoshi Suita; Eiji Yagyu; Yasunori Tokuda

Enhanced performance of RF power modules is required in a next-generation information society. To satisfy these requirements, we designed a novel high-electron mobility transistor (HEMT) structure employing wider bandgap AlGaN for a channel layer, which we called AlGaN channel HEMT, and investigated it. The wider bandgap is more effective for higher voltage operation of HEMTs and contributes to the increase of output power in RF power modules. As a result, fabricated AlGaN channel HEMTs had much higher breakdown voltages than those of conventional GaN channel HEMTs with good pinchoff operation and sufficiently high drain current density without noticeable current collapse. Furthermore, specific on-state resistances of fabricated AlGaN channel HEMTs were competitive with the best values of reported GaN- and SiC-based devices with similar breakdown voltages. These results indicate that the proposed AlGaN channel HEMTs are very promising not only for an information-communication society but also in the power electronics field.


international electron devices meeting | 1995

Giga-bit scale DRAM cell with new simple Ru/(Ba,Sr)TiO/sub 3//Ru stacked capacitors using X-ray lithography

Y. Nishioka; K. Shiozawa; Toshiyuki Oishi; K. Kanamoto; Yasunori Tokuda; H. Sumitani; S. Aya; H. Yabe; K. Itoga; T. Hifumi; K. Marumoto; T. Kuroiwa; T. Kawahara; K. Nishikawa; T. Oomori; T. Fujino; S. Yamamoto; S. Uzawa; M. Kimata; M. Nunoshita; H. Abe

We have fabricated experimental memory cell arrays with a unit cell size of 0.29 /spl mu/m/sup 2/ (0.38 /spl mu/m/spl times/0.76 /spl mu/m). The layout was designed for a half-pitch 8F/sup 2/ cell with 0.14-/spl mu/m process technology, which is promising for 1-gigabit DRAMs and beyond. We developed three advanced technologies for this fabrication. Firstly, synchrotron radiation (SR) X-ray lithography was used to replicate ultra-fine patterns instead of optical lithography. Secondly, we introduced a simple stacked capacitor composed of a metal-organic chemical vapor deposition (MOCVD) grown (Ba,Sr)TiO/sub 3/ (BST) high-dielectric-constant film sandwiched by Ru-metal electrodes. Thirdly, we developed advanced etching techniques for the fine pattern fabrication using improved ECR discharged plasmas, which give less microloading effects.


IEEE Transactions on Electron Devices | 2000

Isolation edge effect depending on gate length of MOSFETs with various isolation structures

Toshiyuki Oishi; Katsuomi Shiozawa; Akihiko Furukawa; Yuji Abe; Yasunori Tokuda

The gate length (L) dependence of the isolation edge effect is investigated for MOSFETs with various isolation structures. We extract the isolation edge effect for a single L by comparing with an H-shaped gate MOSFET which did not have any influence from the isolation edges. For shallow trench isolation (STI), the isolation edge effect is enhanced for L around the onset of the short channel effect (SCE) and is more prominent for a trench edge with a deeper dip. On the other hand, for the local oxidation of silicon (LOCOS) isolation with an elevated field oxide edge (i.e., the birds beak), the isolation edge effect operates in the opposite direction against the cases of STI, though it is enhanced around the SCE appearance point. The L dependence is successfully explained using the charge sharing model where the charge shared by the mixing effect between the SCE and the (inverse) narrow width effect [(I)NWE] is introduced at the channel corners. The enhancement of the isolation edge effect results from that the fraction of the charge shared by the mixing effect depends on L. In addition, the difference between STI and LOCOS occurs because the mixing effect for STI is opposite to that for LOCOS.


IEEE Transactions on Electron Devices | 2004

Effects of interfacial thin metal layer for high-performance Pt-Au-based Schottky contacts to AlGaN-GaN

Naruhisa Miura; Toshiyuki Oishi; Takuma Nanjo; Muneyoshi Suita; Yuji Abe; Tatsuo Ozeki; Hiroyasu Ishikawa; Takashi Egawa

Schottky diodes with Ni-Ti-Pt-Au Schottky electrodes on AlGaN-GaN heterostructures were fabricated and subjected to rapid thermal annealing. The electrical influence on them was investigated in terms of the existence of a thin Ni or Ti layer. The diodes of the Ni-Pt-Au system showed a drastic improvement in their electrical properties, such as an increase in the Schottky barrier height and a decrease in the leakage current, after the 600/spl deg/C treatment whereas the thermal annealing effect was found to be small in the Ti-Pt-Au and the Pt-Au systems. The Ni was considered to play a significant role in realizing a clean Pt contact to AlGaN and reducing surface traps, which were revealed from Auger electron spectroscopy measurement and frequency-dependent capacitance-voltage measurement, respectively. The thermally-treated Ni-Pt-Au gate electrode was concluded to be practicable for realizing high performance HEMTs.


international electron devices meeting | 2007

Remarkable Breakdown Voltage Enhancement in AlGaN Channel HEMTs

Takuma Nanjo; Misaichi Takeuchi; Muneyoshi Suita; Yuji Abe; Toshiyuki Oishi; Yasunori Tokuda; Yoshinobu Aoyagi

We demonstrated a remarkable breakdown voltage enhancement in a new high-electron-mobility transistor (HEMT) with a wider bandgap AlGaN channel layer. A Si ion implantation doping technique was utilized to achieve sufficiently low resistive source/drain contacts. The obtained maximum breakdown voltage was 1650 V with a gate-drain distance of 10 mum. This result is very promising for the further higher-power operation of high-frequency HEMTs.


IEEE Transactions on Electron Devices | 2001

Junction capacitance reduction due to self-aligned pocket implantation in elevated source/drain NMOSFETs

Naruhisa Miura; Yuji Abe; K. Sughihar; Toshiyuki Oishi; T. Furukawa; T. Nakahata; Katsuomi Shiozawa; S. Maruno; Yasunori Tokuda

A new advantage of an elevated source/drain (S/D) configuration to improve MOSFET characteristics is presented. By adopting pocket implantation into an elevated S/D structure which was formed by Si selective epitaxial growth and gate sidewall removal, we demonstrate that the parasitic junction capacitance as well as the junction leakage was significantly reduced for an NMOSFET while maintaining its good short channel characteristics. These successful results are attributed to the modification of the boron impurity profile in the deep S/D regions. The capacitance reduction rate, furthermore, was more remarkable as the pocket dose was further increased. This means that the present self-aligned pocket implantation is very promising for future MOSFETs with a very short gate length, where high pocket dosage will be required to suppress the short channel effect.


compound semiconductor integrated circuit symposium | 2012

Simulation Study and Reduction of Reverse Gate Leakage Current for GaN HEMTs

Y. Yamaguchi; K. Hayashi; Toshiyuki Oishi; Hiroshi Otsuka; T. Nanjo; Koji Yamanaka; Masatoshi Nakayama; Yasuyuki Miyamoto

The two-dimensional effect in the reverse gate leakage current of GaN HEMTs is studied by using the TCAD simulation. At the high voltage region, the extension of the potential from the gate to the drain latterly is important role for the reverse gate leakage current characteristics. On the other hands, the electrons flow vertically from the gate electrode to the GaN channel layer at the low gate voltage. Our model explained excellently the experimental results on wide voltage range from low to 80 V. In addition, we studied the gate annealing process as one of the gate current reduction method.


international symposium on power semiconductor devices and ic's | 2013

Design of enhancement mode single-gate and doublegate multi-channel GaN HEMT with vertical polarity inversion heterostructure

Peijie Feng; Koon Hoo Teo; Toshiyuki Oishi; Koji Yamanaka; Rui Ma

We propose the design and simulation study of novel gallium nitride (GaN) devices, consisting of nitride stacks with different polarity, to provide multiple channels by flexible gate(s) control. Calibrated TCAD device simulations visualize device characteristics of 0.62-μm-gate-length multi-channel transistors. E-mode operations demonstrate a positive small threshold voltage V<sub>th</sub> below 2 V at V<sub>ds</sub> = 0.1 V for all multichannel devices, and a high on-state current I<sub>on</sub> (V<sub>gs</sub> = V<sub>ds</sub> = 4 V) up to 4 A/mm achieved by 4 channels induced within the device.


Archive | 1996

Thin film forming apparatus using laser

Kazuyoshi Kojima; Tetsuya Takami; Kenichi Kuroda; Toshiyuki Oishi; Yukihiko Wada; Akihiko Furukawa


Archive | 1998

Semiconductor device comprising trench isolation insulator film and method of fabricating the same

Katsuomi Shiozawa; Toshiyuki Oishi

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Yasunori Tokuda

Okayama Prefectural University

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Kenichi Ohtsuka

Kawasaki Steel Corporation

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