Travis R. Hebig

1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing

A Ternary Content Addressable Memory (TCAM) uses a two phase search operation where early prediction on its pre-search results prematurely activates the subsequent main-search operation, which is later interrupted only if the final pre-search results contradict the early prediction. This early main-search activation improves performance by 30%, while the low-probability of a late-correct has a negligible power impact. This Early Predict Late Correct (EPLC) sensing enables a high-performance TCAM compiler implemented in 32nm High-K Metal Gate SOI process to achieve 1Gsearch/sec throughput on a 2048×640bit TCAM instance while consuming only 0.76W. Embedded Deep-Trench (DT) capacitance for power supply noise mitigation adds 5% overhead for a total TCAM area of 1.56mm2.

Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable Memory

A memory sense-amplifier timing circuit emulates the behavior of weak memory tail-bits to improve Tail-Bit Tracking (TBT) across Process, Voltage and Temperature. The TBT circuit is used to generate timing for a search operation in a 32nm Ternary Content Addressable Memory (TCAM) compiler resulting in 200mV Vmin improvement at a constant performance, and 50% improved search-time performance at a constant Vmin. This TBT circuit was implemented in 32nm High-K Metal Gate SOI process to achieve 0.60V operation and support up to 1G search/sec throughput on a 2048×640bit TCAM instance.