Igor Arsovski

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

A 64Mb SRAM macro is fabricated in a 32nm high-k metal-gate (HKMG) SOI technology [1]. Figure 14.1.1 shows the 0.154μm2 bitcell (BC). A 2× size reduction from the previous 45nm design [2] is enabled by an equal 2× reduction in BC area. No corner rounding of BC gates allows tighter overlay of gate electrode and active area. The introduction of HKMG provides a significant reduction in the equivalent oxide thickness, thereby reducing the Vt mismatch. This reduction allows aggressive scaling of device dimensions needed to achieve the small area footprint. A 0.7V VDDMIN operation is enabled by three assist features. Stability is improved by a bitline (BL) regulation scheme. Enhancements to the write path include an increase of 40% of BL boost voltage. Finally, a BC-tracking delay circuit improves both performance and yield across the process space.

A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation

A Ternary Content Addressable Memory (TCAM) uses a two-phase search operation where early prediction on its pre-search results prematurely activates the subsequent main-search operation, which is later interrupted only if the final pre-search results contradict the early prediction. This early main-search activation improves performance by 30%, while the low-probability of a late-correct has a negligible impact on power consumption. This Early-Predict Late-Correct (EPLC) sensing with silicon-aware tuning enables a high-performance TCAM compiler implemented in 32 nm High-K Metal Gate SOI process to achieve 1 Gsearch/sec throughput on a 2048×640 bit TCAM instance while consuming only 0.76 W, resulting in an energy efficiency of 0.58-fJ/bit/search. Embedded Deep-Trench (DT) capacitance reduces power supply collapse by 53% while adding only 5% area overhead for a total TCAM area of 1.56 mm2 .

Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories

A memory sense-amplifier self-calibrates during sense-line precharge to reduce the required signal development and minimize data capture timing uncertainty caused by random device variation. When compared to conventional single-ended sensing, this method reduces sense time by 70% and decreases sense-power by 40%. The self-referenced sensing scheme (SRSS) is used to implement the search operation in content-addressable memory (CAM) testchip. Fabricated in 1V 65nm CMOS, this scheme achieves a 0.6ns search time on a 70bit sense-line while consuming only 0.99 fJ/bit/search. Measured search access time on a five bank 64times240bit ternary CAM including selective precharge is 2.2ns. Measured power consumption at 450MHz is 10mW. Hardware shows robust search operation over a voltage range of 0.6V to 1.7V

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

A 64Mb SRAM is fabricated in a 22nm high-performance SOI technology [1]. The ever-increasing integration needs of complex SoC are driving the reduction of SRAM leakage power and increase in memory density. While the area and leakage power benefits of eDRAM continue to be leveraged in applications with large contiguous memory blocks [2], SRAM leakage remains a significant portion of the total SoC power. This work describes an SRAM that is optimized for leakage and performance as top priorities over density. The SRAM features a new bitcell (BC) implemented with a fine-granularity power-gating (FGPG) technique to reduce BC leakage by 37%. FGPG improves leakage reduction by 2× compared to bank-based power-gating (PG) techniques [3-4]. Periphery leakage is also reduced by 40% from the previous design [5] with a low-energy power-supply-partition design that leverages higher Vt devices operating at a higher supply voltage. This scheme alone provides an 8% improvement in performance with a small compromise to the AC power.

1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing

A Ternary Content Addressable Memory (TCAM) uses a two phase search operation where early prediction on its pre-search results prematurely activates the subsequent main-search operation, which is later interrupted only if the final pre-search results contradict the early prediction. This early main-search activation improves performance by 30%, while the low-probability of a late-correct has a negligible power impact. This Early Predict Late Correct (EPLC) sensing enables a high-performance TCAM compiler implemented in 32nm High-K Metal Gate SOI process to achieve 1Gsearch/sec throughput on a 2048×640bit TCAM instance while consuming only 0.76W. Embedded Deep-Trench (DT) capacitance for power supply noise mitigation adds 5% overhead for a total TCAM area of 1.56mm2.

Improved Match-Line Test and Repair Methodology Including Power-Supply Noise Testing for Content-Addressable Memories

This paper describes a novel test and repair methodology for an embedded content-addressable memory (CAM) design. Exhaustive match-line testing is used to ensure correct search operation after manufacturing, while search margin testing is used to provide robust functionality for the life of the product. With CAM being one of the most power-hungry circuits on chip, it is also important to test the effects of CAM-induced power-supply noise. Programmable BIST patterns induce worst-case power-supply noise in the system and then test CAM sensitivity to it. Fails in the CAM are detected by BIST and repaired using row redundancy with word-line and match-line steering. Hardware results stress the importance of this test and repair methodology

Low-noise embedded CAM with reduced slew-rate match-lines and asynchronous search-lines

An embedded content addressable memory (eCAM) uses reduced slew-rate match-line sensing and asynchronous search-line switching to decrease power supply noise while achieving high search speed and low power. When compared to a previous state-of-the-art eCAM, the new design reduces 44% of peak power-supply noise while performing 352M searches/second and consuming 260mW. This reduction in noise directly reduces the amount of decoupling capacitance and, with it, overall chip area. This paper also presents built-in self test patterns for testing search margin and susceptibility to power supply noise. The low-noise eCAM macro has been implemented in 90nm 1.2V CMOS process and is fully functional over a voltage range of 0.7V - 2.05V.

Memory Design Considerations for High-performance Networking SoCs

On chip memory in todays networking SoCs takes up >50% of total area and consumes >40% of total power. As demand for high-performance networks grows, so will the memory content on future SoCs. This paper presents IBMs 32nm HKMG SOI embedded memory offering discussing the considerations associated with the design of key networking memory functions. With memory limiting system performance and dictating minimum voltage system-level power and performance optimization are also presented.

Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable Memory

A memory sense-amplifier timing circuit emulates the behavior of weak memory tail-bits to improve Tail-Bit Tracking (TBT) across Process, Voltage and Temperature. The TBT circuit is used to generate timing for a search operation in a 32nm Ternary Content Addressable Memory (TCAM) compiler resulting in 200mV Vmin improvement at a constant performance, and 50% improved search-time performance at a constant Vmin. This TBT circuit was implemented in 32nm High-K Metal Gate SOI process to achieve 0.60V operation and support up to 1G search/sec throughput on a 2048×640bit TCAM instance.