Treliant Fang

Physical design and assembly process development of a multi-chip package containing a light emitting diode (LED) array die

This paper presents the physical design concept and process developments to construct a small module containing a chip with an array of miniature light emitting diodes (LEDs) as well as the driver control circuitry for the LED array. The module is composed of a glass substrate consisting of a fanout pattern from the I/O bond pads of the fine pitch solder bumped LED array chip. The fanout I/O pattern of the glass terminates on a 40 mil pitch ball grid array land pattern. The LED array chip is bonded face down on the glass and underencapsulated with an optically transparent underfill. All of the driver board circuitry is on a glob top plastic ball grid array (GTPBGA) package whose solder balls are reflow attached to the assembled glass substrate and underencapsulated to provide a finished display module. To implement the module concept, fine pitch (i.e. 80 /spl mu/m) 90Pb/10Sn solder bump technology, fluxless flip chip bonding, thin optically transparent underencapsulation technology had to be developed, as well as the development of a multi-chip 384 I/O 40 mil pitch glob top plastic ball grid array (GTPBGA). The solder balls on the 384 I/O GTPBGA are 30Pb/70In. The assembly technology and underencapsulation technology for the assembly of the glass substrate containing the LED array chip and the 384 I/O GTPBGA also had to be developed.

Squeegee bump technology

An innovative solder bumping technology, termed squeegee bumping, has been developed et Motorolas Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to stencil printing and therefore exhibits better versatility of solder materials selection than the electroplating process. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118/spl plusmn/3.5 /spl mu/m, and a maximum-to-minimum bump height range of 17 /spl mu/m over a 150 mm-diameter wafer have been produced repeatedly on test wafers with 210 /spl mu/m peripheral pitch. A 109.6/spl plusmn/1.3 /spl mu/m bump height on orthogonal array with 250 /spl mu/m pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10/spl times/ reflows and 1008 hours of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55/spl deg/C to +125/spl deg/C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 hours of autoclave stress at 121/spl deg/C, 100%RH, 15 psig test condition.

Environmentally Sound Assembly Processes

The sections in this article are 1 Environmental Awareness 2 Environmentally Benign Materials Selection 3 Assembly Process Considerations 4 Pollution Prevention 5 Product End-Of-Life Management

Development of fluxless flip chip bonding to a thin film multichip module substrate

Motorola SPS has developed an assembly process for a three-chip multichip module using a fluxless bonding technique. The substrate is a 25 mm/spl times/25 mm glass that containing two layers of electroplated metallization with vias connecting the two layers and dielectric layer separating them. A test substrate is designed to characterize the continuity and leakage of the assembled modules. One of the chips has two staggered rows of 384 total bumps on the periphery with 80 /spl mu/m pitch and 45 /spl mu/m bump size. The other two chips have three staggered rows, 222 bumps on each chip, 210 /spl mu/m pitch and 100 /spl mu/m bump size. The bump composition is Pb-Sn with low Sn content. All three chips are bonded to the substrate using a fluxless plasma process followed by reflow in a nitrogen furnace. A high precision robot is used for placement and tacking of the chips on the substrate. After the bonding, the chips are underfilled with a proprietary underfill epoxy, and tested for reliability. All the reliability criteria for the specific application of this module have been met. Physical design and assembly process of this multichip module will be presented.