Tsu-Wei Tseng

ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs

Built-in self-repair (BISR) technique has been widely used to repair embedded random access memories (RAMs). This paper presents a reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations. An efficient redundancy analysis algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISR, a reconfigurable built-in redundancy analysis (ReBIRA) circuit is designed to perform the redundancy algorithm for various RAMs. Also, an adaptively reconfigurable fusing methodology is proposed to reduce the repair setup time when the RAMs are operated in normal mode. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired RAMs to the number of defective RAMs). The area cost of the ReBISR is very small, which is only about 2.7% for four RAMs (one 4 Kbit RAM, one 16 Kbit RAM, one 128 Kbit RAM, and one 512 Kbit RAM). Moreover, the time overhead of redundancy analysis is very small. For example, the ratio of the redundancy analysis time to the test time for a 512 Kbit RAM tested by a March-14 test with solid data backgrounds is only about 0.25%. On the other hand, the proposed fusing scheme can achieve about 86.94% reduction of repair setup time in comparison with a typical fusing scheme for 20 512 × 16 × 64-bit RAMs of which each RAM has one spare row and one spare column.

ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips

Complex system-on-a-chip (SOC) designs usually consist of many memory cores. Efficient yield-enhancement techniques thus are required for the memory cores in SOCs. This paper presents an infrastructure intelligent property (IIP) for testing, diagnosing, and repairing multiple memory cores in SOCs. The proposed IIP can perform parallel testing for multiple memories, and serial diagnosis or repair for one memory each time. In the repair mode, the proposed IIP can execute various redundancy analysis algorithms. Therefore, the user can select a better redundancy analysis algorithm for each memory core being tested according to its redundancy structure. Simulation results show that the proposed IIP needs less test time and redundancy analysis time than the processor-based built-in self-repair scheme. We also have realized the proposed IIP for four types of memories - two 8 K 64 bit SRAMs, one 4 K x 16 bit SRAM, and one 2 K x 32 bit SRAM - based on TSMC 0.18-mum standard cell technology. Simulation results show that the area overhead of the IIP is only about 4.6%.

A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs

This paper presents a reconfigurable built-in self-repair (ReBISR) scheme for multiple repairable RAM cores with different sizes and redundancy organizations (i.e., spare rows/spare columns or spare rows/spare IOs). We also propose an efficient built-in redundancy-analysis (BIRA) algorithm for allocating redundancies for the ReBISR scheme. A reconfigurable BIRA (ReBIRA) circuit is realized to perform the proposed BIRA algorithm for the ReBISR scheme. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). The area cost of the reconfigurable BIRA is very small, e.g., the area cost is only about 1.5% if 512times4times256 design parameters and four memory instances (64times2times32, 128times2times64, 256times4times128, and 512times4times256) are considered. Also, the ratio of the redundancy analysis time to the test time is very small, e.g., the ratio for a 512times4times256-bit memory tested by a March-14N algorithm with solid data backgrounds is only about 0.25%

A Built-In Self-Repair Scheme for Multiport RAMs

Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper presents an efficient BISR scheme for multiport RAMs (MPRAMs). The BISR scheme has a defect-location module (DLM) executing a defect-location algorithm to locate inter-port defects. This enhances the fault-location capability of the applied test algorithm with only a few amount of cost of testing time. A built-in redundancy analyzer (BIRA) executing a proposed redundancy analysis algorithm is also proposed to allocate two-dimension redundancy of MPRAMs. Experimental results show that if a faulty MPRAM has 20% inter-port faults, the DLM can boost the increment of repair rate from 8.4% to 14.4% for different redundancy configurations. The area cost of the BIRA and DLM is small, it is only about 1% for a 4096 times 128-bit MPRAM with 1 spare row and 1 spare IO.

A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs

Embedded memories currently constitute a significant portion of the chip area for typical system-on-chip (SOC) designs. Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper proposes a shared parallel BISR scheme for random access memories (RAMs) in SOCs. The shared parallel BISR can test and repair multiple RAMs simultaneously. A global time-multiplexed built-in redundancy analyzer (TM-BIRA) is used to allocate redundancies of the RAMs under test and repair. We also design a 1500-compatible wrapper for chip-level control of the shared parallel BISR circuits. In comparison with the dedicated parallel BISR scheme (each memory has a self-contained BISR circuit), the proposed parallel BISR scheme can achieve 20% reduction of area cost by paying additional 0.005% test and repair time for serving 5 RAMs with spare rows and spare columns.

A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap

Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-on-chips (SOCs). To increase the utilization of memory redundancy, the BISR technique usually needs to perform built-in redundancy-analysis (BIRA) algorithm for redundancy allocation. This paper presents an efficient BIRA scheme for embedded memory repair. The BIRA scheme executes the 2D redundancy allocation based on the ID local bitmap. This enables that the BIRA circuitry can be implemented with low area cost. Also, the BIRA algorithm can provide good repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories). Experimental results show that the repair rate of the proposed BIRA scheme approximates to that of the optimal scheme for the memories with different fault distributions. Also, the ratio of the analysis time to the test time is small

A Built-in Method to Repair SoC RAMs in Parallel

Built-in-self-repair is an enabling approach for improving memory yield in system-on-chip designs. Reducing the overhead of repair circuits while minimizing the test and repair time is of prime importance. This article presents a fast parallel repair methodology for SoC memory cores and an associated automation framework.

Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs

Built-in self-repair (BISR) techniques are widely used for the repair of embedded memories. One of the key components of a BISR circuit is the built-in redundancy-analysis (BIRA) module, which allocates redundancies according to the designed redundancy analysis algorithm. Thus, the BIRA module affects the repair rate of the BISR circuit. Existing BIRA schemes for RAMs can provide the optimal repair rate (the ratio of the number of repaired RAMs to the number of defective RAMs), but they require either high area cost or multiple test runs. This paper proposes a BIRA scheme for RAMs, which can provide the optimal repair rate using very low area cost and single test run. Furthermore, the BIRA is designed as reconfigurable such that it can be shared by multiple RAMs. Experimental results show that the area cost for implementing the proposed BIRA scheme is much lower than that of existing BIRA schemes with optimal repair rate. A test chip is also implemented to demonstrate the proposed BIRA scheme.

An Infrastructure IP for Repairing Multiple RAMs in SOCs

Modem complex system-on-chips (SOCs) need infrastructure IPs to test, diagnosis, and repair embedded memories. This paper presents an infrastructure IP (IIP) for repairing multiple RAMs in SOCs. The proposed IIP can perform parallel test for multiple memories, and serial diagnosis or repair for one memory each time. Especially, the proposed IIP can execute various redundancy analysis algorithms. We realize the proposed IIP for four memories-based on TSMC 0.18mum standard cell technology. Experimental results show that the area overhead of the IIP is only about 4.6%

A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy

Built-in self-repair (BISR) techniques are widely used for repairing embedded random access memories (RAMs). One key component of a BISR module is the built-in redundancy-analysis (BIRA) design. This paper presents an effective BIRA scheme which executes the 2-D redundancy allocation based on a 1-D local bitmap. Two BIRA algorithms for supporting two different redundancy organizations are also proposed. Simulation results show that the proposed BIRA scheme can provide high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) for the RAMs with different fault distributions. Experimental results show that the hardware overhead of the BIRA design is only about 2.9% for an 8192 × 64-bit RAM with two spare rows and two spare columns. Also, the ratio of the BIRA analysis time to the test time is only about 0.02% if the March-CW test is performed. Furthermore, a simulation flow is proposed to determine the size of the 1-D local bitmap such that the BIRA algorithm can provide the best repair rate using the smallest-size 1-D local bitmap.