Yu-Jen Huang

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18µm CMOS technology for a 16×32 TSV array in which each TSV cell size is 45µm2 is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.

Yield-enhancement techniques for 3D random access memories

Three-dimensional (3D) integration technology using through silicon via (TSV) is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for using the 3D integration technology. Introducing redundancies into a large-capacity RAM in design phase is essential for yield improvement. In this paper, we present yield-enhancement techniques for 3D RAMs. In addition to typical redundancy schemes are used to improve the yield of 3D RAMs, an inter-die redundancy scheme is proposed. Also, a stacking flow is proposed to further improve the final yield of 3D RAMs with the proposed inter-die redundancy scheme.

Built-In Self-Repair Scheme for the TSVs in 3-D ICs

3-D integration using through-silicon-via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. Test and yield are two big issues for volume production of 3-D ICs. In this paper, we propose a built-in self-repair (BISR) scheme to test and repair TSVs in 3-D ICs. The BISR scheme, arranging the TSVs into arrays similar to memories, can effectively enhance the yield of TSVs in a 3-D IC such that the yield of the 3-D IC is boosted. Furthermore, a global fusing methodology is proposed to reduce the requirement of fuses. Simulation and analysis results show that the proposed BISR scheme can drastically reduce the area cost and test time in comparison with an existing TSV repair scheme for the same final yield of TSVs under repair. For a 3-D wide-IO DRAM with 512 TSVs, for example, the proposed repair scheme can achieve 32.4% area reduction and 73.4% test time reduction.

A Built-In Self-Repair Scheme for Multiport RAMs

Built-in self-repair (BISR) techniques have been widely used for enhancing the yield of embedded memories. This paper presents an efficient BISR scheme for multiport RAMs (MPRAMs). The BISR scheme has a defect-location module (DLM) executing a defect-location algorithm to locate inter-port defects. This enhances the fault-location capability of the applied test algorithm with only a few amount of cost of testing time. A built-in redundancy analyzer (BIRA) executing a proposed redundancy analysis algorithm is also proposed to allocate two-dimension redundancy of MPRAMs. Experimental results show that if a faulty MPRAM has 20% inter-port faults, the DLM can boost the increment of repair rate from 8.4% to 14.4% for different redundancy configurations. The area cost of the BIRA and DLM is small, it is only about 1% for a 4096 times 128-bit MPRAM with 1 spare row and 1 spare IO.

A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines

This paper proposes a Pai-Sigma matchline scheme to reduce the compare (search) power of a ternary content addressable memory (TCAM). The proposed matchline does not incur the issues of charge sharing and short circuit current, which typically exist in the hybrid nand-nor matchline. Moreover, the switching activity of the search lines of a TCAM with the proposed matchlines is low. A 32×64-bit TCAM with the Pai-Sigma matchlines is implemented to demonstrate the low-power feature. Results show that the compare power of the TCAM can achieve 60% energy reduction compared with the conventional nor-type TCAM. Also, the energy consumption per bit per search of the TCAM is only 2.287 fJ/bit/search.

Post-bond test techniques for TSVs with crosstalk faults in 3D ICs

Three-dimensional (3D) integration is expected to cope with the difficulties faced by current 2D system-on-chip designs using through silicon via (TSV). However, coupling capacitance exists between two neighboring TSVs such that TSVs are prone to crosstalk faults. In this paper, we propose a builtin self-test (BIST) scheme for the post-bond test of TSVs with crosstalk faults in 3D ICs. A test algorithm for testing crosstalk faults of TSVs is proposed. The proposed BIST scheme has the feature of low area cost. Simulation results show that the area overhead of the BIST circuit implemented with 90nm CMOS technology for a 512×16 TSV array in which each TSV cell size is 15 × 15μm2 is 6.7%.

A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability

This paper presents a design methodology of reconfigurable hybrid carry lookahead/carry select adders (CLSA). A novel partition scheme is used to divide a large hybrid CLSA into multiple small ones with blocking specific inputs of the carry lookahead unit in the hybrid CLSA. The partition scheme incurs no delay penalty regardless of the size of adders. Moreover, the additional area cost is very small. For example, a reconfigurable 16-bit hybrid CLSA with four different partition configurations needs additional 6 two-input AND gates and three two-input multiplexers. Simulation results show that the delay of a 64-bit reconfigurable CLSA is only about 1.38 ns in 0.18 /spl mu/m technology.

A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy

Built-in self-repair (BISR) technique is a popular method for repairing defective embedded memories. To allocate redundancy efficiently, built-in redundancy-analysis (BIRA) component is a core component in a BISR design. This paper presents a BIRA scheme for RAMs with two-level redundancy, i.e., spare rows, spare columns, and spare words. A compressed local bitmap is used to collect faulty information for redundancy allocation. Then an efficient redundancy analysis algorithm based on the compressed local bitmap is proposed to allocate redundancy. Experimental results show that the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the proposed redundancy analysis algorithm approaches to that of the exhaustive search algorithm. Also, area overhead of the proposed BIRA scheme is low. It is only about 2% for an 8K × 64-bit RAM with three spare rows, three spare columns, and two spare words.

DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs

Built-in self-repair (BISR) techniques are widely used to enhance the yield of embedded random access memories (RAMs). Fault-location ability of test algorithms executed by a BISR circuit has heavy impact on the repair efficiency of the BISR circuit. This paper proposes a defect-aware BISR (DABISR) scheme for single-port RAMs (SPRAMs) and multi-port RAMs (MPRAMs) in system chips. Multiple RAMs can share a DABISR such that the area cost of DABISR is drastically reduced. We also present two defect-location algorithms (DLAs) for identification of bridge defects between word-lines and bit-lines of MPRAMs. The DABISR can perform DLAs to locate bridge defects such that it can provide high repair efficiency. For example, simulation results show that if a faulty two-port RAM has 20% inter-port faults, the DLAs can help to gain 8.4-14.4% increase of repair rate for different redundancy configurations. In comparison with an existing shared BISR scheme, however, the DABISR only incurs about 0.34% additional area overhead to support the function of DLAs.

Testability Exploration of 3-D RAMs and CAMs

Three-dimensional (3-D) integration is an emerging integrated circuit technology. It offers many advantages over the 2-D integration. However, testing 3-D chips is a very challenging job. The testing of a 3-D chip includes the testing for known good die (KGD) and the testing of stacked 3-D chip. This paper analyzes the test complexities of 3-D random access memories (RAMs) and content addressable memories (CAMs) in the phase of testing of stacked 3-D ICs with functional faults. Analysis results show that the 3-D CAMs and RAMs can be tested with lower test complexity than the 2-D ones. Furthermore, simple design-for-testability (DFT) methods are proposed to reduce the test complexity of 3-D RAMs and CAMs further.