Tsukasa Oishi

A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme

A high-density and high-speed memory cell named 1-transistor 4-magnetic tunnel junction (1T-4MTJ) has been proposed for magnetic random access memory (MRAM). The new 1T-4MTJ cell has been successfully demonstrated by a 1 Mb MRAM test device, using a 130 nm CMOS process. The sensing scheme of a self-reference sense amplifier with Voltage offset (SRSV) enables high-speed memory operation (access time) of tAC=56 nsec and 50 MHz@4cycle.

A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture

A 1Mbit MRAM with a 0.81 /spl mu/m/sup 2/ 1-Transistor 1-Magnetic Tunnel Junction (1Tr-1MTJ) cell using 0.13 /spl mu/m 4LM logic technology has been produced. A folded-bitline sensing and common write word-line scheme with dummy row architecture achieves 100MHz random read cycle with n/sup +/ diffusion/Co-silicide read source lines. Employing a distributed gate voltage control scheme, high speed write current switching without write disturb by peak current even at 1.2V power supply is demonstrated.

0.5 V Start-Up 87% Efficiency 0.75 mm² On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration

An on-chip low power single-inductor dual-output (SIDO) DC-DC boost converter is proposed for battery and solar cell operating sensor network applications. A proposed feed forward control determines the Ton/Toff ratio precisely for each output without any compensation or linear capacitor. This feature helps reduce the costs of the external components and utilize an inexpensive process technology. A test chip was fabricated by 190-nm flash-memory embedded micro-computers CMOS process technology and can achieve an efficiency of 87% with a small area size of just 0.75 mm2. For solar cell operation, a 0.5 V start-up was achieved even with a high threshold voltage of 0.7 V with a proposed forward back biased charge pump. A constant voltage algorithm was implemented as a maximum power point tracking (MPPT) control. With this MPPT control, a solar cell with an open voltage of 1.03 V and a short current of 83 mA was able to charge a super capacitor of 0.4 F up to 5 V within 80 s.

An 8kB EEPROM-Emulation DataFLASH Module for Automotive MCU

An 8 kB E2FLASH test-chip is fabricated and reliability tests are executed. The paper shows the P/E cycle dependence of the threshold-voltage distribution and program/erase time. The threshold-voltage distribution does not degrade, and maintains enough margin to the wordline level (4.5 V) even after 1M P/E cycles. Erase time is 10 ms/block (average) for the first P/E cycle and 20 ms/block (average) after 1M P/E cycles. This is almost the same erase performance as on-board EEPROM, due to the DCNOR structure that does not use the read channel during program operation. On the other hand, program time increase is caused by charge trapping at tunnel oxide, but program time is 500 mus/word (average) even after 1M P/E cycles. The threshold-voltage shift value is only -1V after 1000 hr bake at Ta = 250 degC. These results indicate that the 8 kB E2FLASH is able to replace on-board EEPROM.

Design of a low power NoC router using Marching Memory Through type

Power consumption of Network-on-Chip (NoC) is becoming more important in many core processors. Input buffers utilized in routers consume a significant part of the total power of NoCs. In order to reduce this power consumption, a novel power efficient memory called Marching Memory Through type (MMTH) is introduced. By connecting transparent latches in tandem, MMTH achieves high speed operation with a low power consumption. MMTH, however, requires a certain overhead at read operation, and hence we propose a latency reduction scheme based on the look-ahead routing. The proposed router was designed in Renesass 40nm process and compared with a standard router using conventional register-based FIFOs in terms of the network performance, application performance, and power consumption. The result of evaluation shows that the proposed router reduces the power consumption by 42.4% on average at 2GHz and the expense of only 0.5-2.0% performance overhead.

A 0.5V start-up 87% efficiency 0.75mm 2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration

An on-chip low power single-inductor dual-output DC-DC converter is proposed for battery and solar cell operating sensor network applications. By a new feed-forward control, a test chip fabricated by 190nm CMOS achieves a high efficiency of 87% at the practical load condition with a small area size of 0.75mm2 without any compensation capacitor. In addition, the fluctuation of the output voltage remains within 100mV when the input voltage changes from 1V to 2V. For a solar cell operation, 0.5V start-up is achieved with a process technology of flash-memory embedded micro-computers by utilizing forward back bias. A super capacitor is charged up to 5V from a solar cell with an implemented MPPT.

A low power NoC router using the marching memory through type

We have concluded that with a router using MMTH the power consumption is associated with the bit change rate of the data, and when NAS parallel benchmarks work on NoC, it is reduced by 42.4% on average at 2GHz compared with a traditional FIFO implementation. The performance degradation caused by the delay of the reading time can be mostly saved by the look-ahead technique in the router.

Wide input range from 80mV to 3V operation on-chip single-inductor dual-output (SIDO) DC-DC boost converter with self-adjusting clock duty for sensor network applications

An SIDO boost DC-DC converter operating with a wide input voltage range is proposed for sensor network applications. As the input voltage becomes lower, the inductor current is restricted by on-resistance of a driver transistor. Therefore, longer Ton period does not indicate a lager inductor current. In this condition, Ton period for the lowest input voltage operation is determined as the inductor current reaches 85% of its ideal value. The converter should operate in a continuous conduction mode (CCM) to obtain the maximum power from the input. Toff period is set by feed forward control from Ton period to sustain the output voltages. A test chip fabricated by a 190nm CMOS technology operates at the input voltage range from 80mV to 3V with maintaining the two output voltages of 3V and 5V, respectively. This means that the power of 625μW is substantially supplied from the input of 80mV for inner circuits.

On-chip single-inductor dual-output DC-DC boost converter having dual output/input modes for utilizing external power transistor drive and micro-computer controlled MPPT

A compact on-chip SIDO DC-DC converter is proposed for portable equipments operating with a battery or a solar cell. A current up to 30mA is supplied with own transistors in an internal drive mode and more than 100mA by utilizing external power transistors in an external drive mode. The efficiencies are 85% and 84% for each case. A cross regulation problem is solved by inserting an extra cycle before switching the outputs. For solar cell operation, two features are implemented. Any kind of maximum power point tracking MPPT is available by receiving a clock signal calculated by a micro-computer. The converter exploits 99% of the expected maximum power of a solar cell. Backward current protection reduces a leak current by three orders without any performance losses when the light is not available like as in the night.

0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers

This paper presents embedded use DC-DC boost converters for battery operating micro-computers. Pulse frequency modulation (PFM) is employed for fast response. A new control method is applied to improve the efficiency by regulating the inductor current optimally from both of input voltage and load current. A synchronous rectifier converter fabricated by a 180nm CMOS technology achieves the efficiency of 92% at the condition of 1.5V input voltage and 20mA load current as predicted through a model analysis. The efficiency is improved more than 15% compared with the case of ILmax being a fixed value.