Tsunaki Takahashi

Thermal-aware device design of nanoscale bulk/SOI FinFETs: Suppression of operation temperature and its variability

The self-heating effects in Bulk/SOI FinFETs have been systematically investigated and compared. It is demonstrated that lattice temperature is significantly lower in Bulk FinFETs owing to the larger heat dissipation to the Si substrate. Heat dissipation paths in Bulk/SOI FinFETs have been studied and the device-parameter dependence of thermal characteristics has been analyzed. It is demonstrated that the Bulk FinFETs show greater temperature fluctuations resulting from device parameter variations. The fluctuation can be greatly suppressed by miniaturizing the extension length. It is shown that the impact of thermal resistance at the MOS interface is more significant in SOI FinFETs than in Bulk FinFETs.

Self-Heating Effects and Analog Performance Optimization of Fin-Type Field-Effect Transistors

The self-heating effects (SHEs) of bulk and silicon-on-insulator (SOI) fin-type field-effect transistors (FinFETs) and their impacts on circuit performance have been investigated on the basis of a realistic thermal conductivity of silicon. The heat dissipation via interconnect wires and interface thermal resistance in the high-κ gate stack were incorporated in simulations. It is shown that the depth of the shallow trench isolation (STI) of bulk FinFETs cannot be decreased to less than 100 nm owing to the increase in off-state leakage current. We observed that the thermal resistance Rth of SOI FinFETs greatly decreases upon thinning the buried oxide (BOX) layer. When the BOX thickness tBOX is less than 50 nm, the Rth of SOI FinFETs is smaller than that of bulk FinFETs with an STI thickness of 100 nm, indicating a lower operation temperature of the thin-BOX SOI FinFETs than that of bulk FinFETs. The lower operation temperature of the 5-nm BOX SOI FinFET was confirmed under a practical bias condition for analog operations. In fin width, Wfin, versus Rth characteristics, a strong Wfin dependence of Rth was observed only in the bulk FinFETs, implying that fluctuations in Wfin result in the variability of the operation temperature of the bulk FinFETs. Analog performance has been analyzed by calculating the cutoff frequency fT and the maximum oscillation frequency fmax. We demonstrated that both fT and fmax can be maximized in SOI FinFETs by optimizing tBOX with regard to electrical and thermal properties. Better analog performance, and hence the optimization of tBOX, are indispensable for the device design of a FinFET-based system-on-a-chip (SoC) platform.

A new pulsed cryogenic proton source cooled by liquid helium

A new cryogenic proton source with liquid helium cooling system is presented. The anode is cooled down to about 4.2 K. A hydrogen ice is produced on the surface and used as the ion source. Proton beams of a current density 21 A/cm2 at 200 kV are extracted with good reproducibility. This new ion source is expected to be a proton source without contamination by nonprotonic ions.

Impact of Gate Poly Depletion on Evaluation of Channel Temperature in Silicon-on-Insulator Metal--Oxide--Semiconductor Field-Effect Transistors with Four-Point Gate Resistance Measurement Method

Self-heating effects (SHEs) in silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is evaluated and an accurate measurement method for device temperature is developed using the four-point gate resistance measurement method. Although the method of using a polysilicon gate as a temperature sensor was proposed more than 20 years ago, the accuracy of the technique has not been checked. In this work, it is demonstrated that the channel temperature estimated by the conventional method is not accurate under some special conditions. The measurements of gate resistance under various biases revealed that the depletion of the polysilicon gate had a significant impact on gate resistance. We propose a method of accurately evaluating channel temperature, where the effect of poly depletion is successfully subtracted. At an input power of 5 mW the increase in channel temperature is approximately 30 K, corresponding to a thermal resistance of 6.0 K W-1 m-1.

Comparison of self-heating effect (SHE) in short-channel bulk and ultra-thin BOX SOI MOSFETs: Impacts of doped well, ambient temperature, and SOI/BOX thicknesses on SHE

Self-heating effects (SHEs) of bulk and SOI FETs including 6-nm ultra-thin (UT) BOX devices are systematically investigated and compared using the four-terminal gate resistance technique. For bulk FETs, it has been verified for the first time that the SHE is not negligible in nanoscale devices mainly owing to a decrease in the thermal conductivity of the more heavily doped well. Furthermore, it has been demonstrated that the magnitude of the SHE strongly depends on the chip (ambient) temperature (Tchip). For SOI FETs, the impacts of BOX/SOI thinning are evaluated and explained in terms of the thermal conductivities of materials within heat dissipation paths. It has been demonstrated that the device temperature of 6-nm UT BOX SOI FETs is close to that of bulk FETs at Tchip under operating conditions. A thermal-aware device design of the UT Body and BOX (UTBB) structure is proposed on the basis of the evaluated BOX/SOI thickness dependences of the SHE. The SHE of UTBB FETs with a raised source/drain and/or shorter contact pitch could be comparable to that of bulk FETs in deeply scaled nodes. In addition, the doping concentration under the BOX should be optimized in order to achieve low and Tchip-independent SHE.

Experimental evidence of increased deformation potential at MOS interface and its impact on characteristics of ETSOI FETs

Deformation potential (Dac), which determines the strength of electron-phonon scattering, is one of the most important physical parameters of Si. A longstanding unresolved question in Dac is that Dac for MOSFETs is considered to be much greater than Dac for bulk Si. In this work, we have demonstrated for the first time that Dac increases sharply at MOS interfaces within several-nm range. Because of the enhanced Dac at MOS interface, Dac for nanoscale SOI channel is expected to be increased owing to the high surface-to-volume ratio, which is verified by electron mobility calculations in extremely-thin SOI (ETSOI) MOSFETs and experimental stress-induced mobility enhancement in nanoscale SOI.

Experimental Study on Electron Mobility in Accumulation-Mode Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

Junctionless, or accumulation-mode, metal–oxide–semiconductor field-effect transistors (MOSFETs), where the channel and source/drain doping types are the same, have attracted growing interests because of their simpler fabrication processes. However, carrier transport properties, in particular, mobility characteristics, in the junctionless silicon-on-insulator (SOI) MOSFETs have been less studied. Although higher mobility in accumulation-mode SOI MOSFETs has been reported, the physical mechanisms of the higher mobility have not yet been clarified. In this work, the physical mechanisms of higher mobility in accumulation-mode MOSFETs have been investigated. We fabricated junctionless SOI MOSFETs with a channel doping concentration of 1×1017 cm-3 and an SOI body thickness of 48 nm whose mobility is greater than the bulk universal mobility in spite of the high doping concentration in the channel. The drain current consists of two components: one in the accumulation layer and the other in the SOI body. The mobility of each component is evaluated separately. As a result, it is revealed that the total mobility is the weighted mean of the two mobility components, where carrier concentration is the weight.

Methodology for Evaluating Operation Temperatures of Fin-Type Field-Effect Transistors Connected by Interconnect Wires

A new methodology for evaluating operation temperatures of transistors connected by interconnect wires is developed. Thermal characteristics of fin-type field-effect transistors (FinFETs) and interconnect wires are modeled using simple equivalent thermal circuits. The temperature nodes are the source, drain, gate, substrate, and hot spot, where the lattice temperature is the highest. By calculating heat flows from the hot spot to the other four nodes, the thermal resistances Rths for bulk and silicon-on-insulator (SOI) FinFETs are extracted. It is shown that the source Rth is higher than the drain Rth because of asymmetric temperature distributions in the device. The thermal resistances of interconnect wires and vias are given as analytical expressions. By combining the device Rths and the analytical Rths for the interconnect wires and vias, device temperatures can be obtained. The validity of the proposed methodology was confirmed by temperature simulations of a circuit where two devices were connected in parallel. It is demonstrated that high-thermal-conductivity interconnect materials, such as carbon nanotubes, are effective for lowering device temperatures when interconnects are extremely downscaled such as systems at the 14 nm technology node.

Anomalous electron mobility in extremely-thin SOI (ETSOI) diffusion layers with SOI thickness of less than 10 nm and high doping concentration of greater than 1×10 18 cm −3

Carrier transport in heavily doped extremely thin silicon- on-insulator (ETSOI) diffusion layers with SOI thickness of less than 10 nm was thoroughly studied. We found that electron mobility ( µ<inf>e</inf>) in heavily doped ETSOI diffusion layer is totally different from µ<inf>e</inf> in heavily doped bulk Si. In ETSOI diffusion layers with SOI thickness ranging from 5 nm to 10 nm µ<inf>e</inf> is enhanced, compared with µ<inf>e</inf> in heavily doped bulk Si. This enhancement is caused by the reduced number of ions which interact with carriers in ETSOI. On the other hand, in ETSOI with SOI thickness of less than 2 nm µ<inf>e</inf> is degraded, compared with µ<inf>e</inf> in heavily doped bulk Si. The degradation is primary due to the scattering induced by SOI thickness fluctuations. µ<inf>e</inf> in heavily doped ETSOI with SOI thickness of less than 2 nm is further decreased as doping concentration increases, which results from the enhanced potential fluctuations by Coulomb potentials made by randomly distributed ions.

Pulsed ion beam generation with cryogenic‐anode diode

Magnetically insulated ion diodes with a cryogenically refrigerated anode are proposed and their characteristics are examined. Proton beams of 7 A/cm2 and deuteron beams of 5 A/cm2, with energy of about 80 keV are extracted from a refrigerated H2O or D2O anode with good reproducibility and reasonable repetition rate.