Ken Uchida

Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm

The electrical characteristics of ultrathin-body SOI CMOSFETs with SOI thickness ranging from 2.3 nm to 8 nm are intensively investigated. As a result, it is demonstrated, for the first time, that electron mobility increases as SOI thickness decreases, when SO, thickness is in the range from 3.5 nm to 4.5 nm. In addition, it is demonstrated that, when SOI thickness is thinner than 4 nm, slight (even atomic-level) SOI thickness fluctuations have a significant impact on threshold voltage, gate-channel capacitance, and carrier mobility of ultrathin-body CMOSFETs.

Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique

A novel approach for achieving high-performance Schottky-source/drain MOSFETs (SBTs: Schottky Barrier Transistors) is proposed. The dopant segregation (DS) technique is employed and significant modulation of Schottky barrier height is demonstrated. The DS-SBT fabricated with the current CoSi/sub 2/ process show competitive drive current and better short-channel-effect immunity compared to the conventional MOSFET. In conclusion the DS-Schottky junction is useful for the source/drain of advanced MOSFETs.

Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime

The physical mechanisms of mue enhancement by uniaxial stress are investigated. From full band calculations, uniaxial-stress-induced split of conduction band edge, DeltaEC and effective mass change, Deltam*, are quantitatively evaluated. It is experimentally and theoretically demonstrated that the energy surface of 2-fold valleys in Si (001) FETs is warped due to uniaxial lang110rang stress, resulting in lighter mT of 2-fold valleys parallel to the stress. By using calculated DeltaEC and Deltam*, experimental (ie enhancement is accurately modeled for biaxial, uniaxial lang100rang, and uniaxial lang110rang stress. The limits of mue enhancement and the effectiveness of uniaxial stress engineering in enhancing nFET ballistic Id,sat are also discussed

Non-volatile Si quantum memory with self-aligned doubly-stacked dots

We propose a novel Si dot memory whose floating gate consists of self-aligned doubly stacked Si dots. A lower Si dot exists immediately below an upper dot and lies between thin tunnel oxides. It is experimentally shown that charge retention is improved compared to the usual single-layer Si dot memory. A theoretical model considering quantum confinement and Coulomb blockade in the lower Si dot explains the experimental results consistently, and shows that charge retention is improved exponentially by lower dot size scaling. It is shown that the retention improvement by lower dot scaling is possible, keeping the same write/erase speed as single dot memory, when the tunnel oxide thickness is adjusted simultaneously.

Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-body metal-oxide-semiconductor field-effect transistors

We demonstrate that carrier scattering induced by the thickness fluctuation of a silicon-on-insulator (SOI) film reduces electron mobility in ultrathin-body metal–oxide–semiconductor field-effect transistors with SOI thickness, TSOI, of less than 4 nm at room temperature and is the dominant scattering mechanism at low temperatures. The thickness fluctuation of a nanoscaled SOI film induces large potential variations due to the difference of quantum-confinement effects from one part to another, and thus carrier scattering potentials are formed in the channel. It is shown that experimental electron mobility follows the theoretical TSOI dependence and the expected temperature dependence of the scattering induced by SOI thickness fluctuation.

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.

Programmable single-electron transistor logic for future low-power intelligent LSI: proposal and room-temperature operation

This paper proposes, for the first time, the concept of programmable logic circuit realized with single-electron transistors (SETs). An SET having nonvolatile memory function is a key element for the programmable SET logic. The writing and erasing operations of the nonvolatile memory function make it possible to tune the phase of Coulomb oscillations. The half-period phase shift induced by the memory function makes the function of SETs complementary to that of the conventional SETs. As a result, SETs having nonvolatile memory function have the functionality of both the conventional (nMOS-like) SETs and the complementary (pMOS-like) SETs. By utilizing this fact, the function of SET circuits can be programmed with great flexibility, on the basis of the information stored by the memory functions. We have successfully fabricated SETs that operate at room temperature and observed the highest room-temperature peak-to-valley current ratio of Coulomb oscillations. The operation of the programmable SET logic is demonstrated using the room-temperature operating SETs. This is the first demonstration of room-temperature SET logic operation. The proposed programmable SET logic provides the potential for low-power, intelligent LSI chips suitable for mobile applications.

A unified simulation of Schottky and ohmic contacts

The Schottky contact is an important consideration in the development of semiconductor devices. This paper shows that a practical Schottky contact model is available for a unified device simulation of Schottky and ohmic contacts. The present model includes the thermionic emission at the metal/semiconductor interface and the spatially distributed tunneling calculated at each semiconductor around the interface. Simulation results of rectifying characteristics of Schottky barrier diodes (SBDs) and resistances under high impurity concentration conditions are reasonable, compared with measurements. As examples of application to actual devices, the influence of the contact resistance on salicided MOSFETs with source/drain extension and the immunity of Schottky barrier tunnel transistors (SBTTs) from the short-channel effect (SCE) are demonstrated.

High-performance 50-nm-gate-length Schottky-source/drain MOSFETs with dopant-segregation junctions

High-performance operation was achieved in a novel Schottky-source/drain MOSFET (SBT: Schottky barrier transistor), which has dopant-segregation (DS) Schottky source/drain. Sub-100 nm complementary DS-SBTs were fabricated using the CoSi/sub 2/ process, which was fully compatible with the current CMOS technology. Excellent CMOS performance was obtained without any channel-mobility degradation, and CMOS ring oscillator was successfully demonstrated. In addition, >20 % improvement in drive current over the conventional n-MOSFETs was confirmed in the n-type DS-SBTs around the gate length of 50 nm.

Experimental study on carrier transport mechanisms in double- and single-gate ultrathin-body MOSFETs - Coulomb scattering, volume inversion, and /spl delta/T/sub SOI/-induced scattering

The carrier transport mechanisms in single- and double-gate UTB MOSFETs are investigated. It is demonstrated that Coulomb scattering in UTB MOSFETs is greater than that in thicker body MOSFETs. It is found that, in higher Ns regions, the mobility of double-gate structures is smaller than that of single-gate structures in 4.3-nm body MOSFETs, which is due to the SOI-thickness-fluctuation-induced scattering. It is also demonstrated that Coulomb scattering is greatly suppressed in double-gate MOSFETs. The electrical characteristics of sub-1-nm body MOSFETs are also investigated.