Tsuneo Nakata

CTL model checking based on forward state traversal

We present a CTL model checking algorithm based mainly on forward state traversal, which can check many realistic CTL properties without doing backward state traversal. This algorithm is effective in many situations where backward state traversal is more expensive than forward state traversal. We combine it with BDD-based state traversal techniques using partitioned transition relations. Experimental results show that our method can verify actual CTL properties of large industrial models which cannot be handled by conventional model checkers.

Automatic test program generation for pipelined processors

Simulation-based verification has both advantages and disadvantages compared with formal verification. Our demand is to find a practical way to verify actual microprocessors. This paper presents an efficient test program generation method for simulation-based verification using techniques developed for formal verification. Our test program generator enumerates all reachable states of a processor pipeline and generates instruction sequences for every reachable test care. The program covers complicated test cases that are difficult to cover with random instructions and impossible to cover with conventional test program generation methods. Our test program generator also works for larger microprocessor designs than formal verifiers have done.

Forward model checking techniques oriented to buggy designs

Forward model checking is an efficient symbolic model checking method for verifying realistic properties of sequential circuits and protocols. In this paper, we present the techniques that modify the order of state traversal on forward model checking, and that dramatically improve average CPU time for finding design errors. A failing property has to be checked again and again to analyze the bug until it is corrected. The techniques, therefore, can have significant impacts on actual verification tasks. We use a modified regular/omega-regular expression to represent a set of illegal state transition sequences of an FSM. It makes the problem clear and gives us a sense of depth-first traversal, not on the state space, but on the property.

An object-oriented design process for system-on-chip using UML

The object-oriented design process has been a hot topic in software development since it will improve product quality and productivity significantly, which is also a major issue in system-on-chip design. In this paper, a design process is proposed for hardware-software heterogeneous systems by reinforcing parallelism, structure, and timing. The management of design abstraction is also introduced for refinement of hardware. UML is used as a modeling language, and the reinforcement above is gracefully integrated into UML by its extensibility mechanism. An example of architecture exploration and performance analysis is illustrated through the application of the process to an image decoding design.

A method of static compaction of test stimuli

Large numbers of test stimuli impact on test application time and cost of test application. Hence there is the need to keep numbers of test stimuli low while maintaining as high fault coverage as possible. In this paper, static compaction of test stimuli is seen as a minimization problem. The task of static compaction of a set of test stimuli has been formulated as a minimum covering problem. Based on the concept of minimization, a method of static compaction has been developed. Results of experiments conducted to evaluate the method are also presented. The method achieved a significant compaction of sets of test stimuli that had previously been compacted by means of a test generation algorithm that features dynamic compaction.

Integrating UML into SoC Design Process

In this paper, we propose a method for integrating UML model into the current SoC design process. UML is introduced as a formal model of specification for SoC design. The consistency and completeness of the specification is validated based on the formal UML model. The implementation is validated by a systematic derivation of test scenarios from the UML model. The method has been applied to the design of a new media-processing chip for mobile devices. The application of the method shows that it is not only effective for finding logical errors in the implementation, but also eliminates errors due to inconsistency and incompleteness of the specification.

Functional Verification of System on Chips-Practices, Issues and Challenges

Summary form only given. In a complex SoC design flow functional verification is very important; any behavioral or functional bug escaping this phase will not be detected in the subsequent implementation phases and will surface only after the first silicon is integrated into the target system, resulting in costly design and silicon iterations. A number of academic and industrial research laboratories have been carrying out research on functional verification of SoCs based on different approaches. Many of the issues relate to intrinsic limitations of some of the approaches taken; while others have to do with the quality of the design information, by way of design descriptions, design documentations and design specifications, from which the overall verification objectives are derived. SoCs have brought to focus the need to carry out design and verification concurrently. For the design and verification task to proceed concurrently there is a need to capture formally, design information and implementation details at various levels of abstraction. As designs become more complex, functional verification will have to be carried out using the divide and conquer approach. We discuss several approaches based on compositional verification.

Behavioral design and test assistance for pipelined processors

The authors propose a new concept in designing and testing processors. This approach generates behavioral-level test environments in VHDL for specific processor mechanisms, including automatic generations of test programs and behavioral descriptions. The authors have implemented an application to pipeline controllers.<<ETX>>

Automatic program generator for simulation-based processor verification

This paper presents an efficient test program generator for logic simulation that uses techniques developed for formal verification. Our test program generator enumerates all reachable states of a processor pipeline and generates instruction sequences for any reachable test case. The program covers all complicated test cases that are difficult to cover with random instructions and are impossible to cover by conventional test program generation methods.<<ETX>>

Formal verification based on assume and guarantee approach: a case study

In this paper, we present a verification case study of the Audio Output Interface (AOF) subsystem based on a compositional verification approach known as the Assume-Guarantee approach. We illustrate how designers can leverage their detailed knowledge of a design to partition it at the module level, and, thereby, enable the Assume-Guarantee approach to overcome intrinsic limitations of a formal verification tool to successfully verify large designs.