Fumiyasu Hirose

CTL model checking based on forward state traversal

We present a CTL model checking algorithm based mainly on forward state traversal, which can check many realistic CTL properties without doing backward state traversal. This algorithm is effective in many situations where backward state traversal is more expensive than forward state traversal. We combine it with BDD-based state traversal techniques using partitioned transition relations. Experimental results show that our method can verify actual CTL properties of large industrial models which cannot be handled by conventional model checkers.

Automatic test program generation for pipelined processors

Simulation-based verification has both advantages and disadvantages compared with formal verification. Our demand is to find a practical way to verify actual microprocessors. This paper presents an efficient test program generation method for simulation-based verification using techniques developed for formal verification. Our test program generator enumerates all reachable states of a processor pipeline and generates instruction sequences for every reachable test care. The program covers complicated test cases that are difficult to cover with random instructions and impossible to cover with conventional test program generation methods. Our test program generator also works for larger microprocessor designs than formal verifiers have done.

Efficient Placement and Routing Techniques for Master Slice LSI

This paper deals with placement and routing techniques for master slice LSIs. The basic idea of both techniques is to make wiring density on the chip more uniform. Algorithms and some experimental results are described.

Simulation processor “SP”

The continuing development of large-scale and complicated computer systems has created an increasing demand for fast logic simulation which can locate errors in the logic design. The authors have devised a new scheme which makes use of memory instead of registers in controlling the pipeline system. This idea formed the basis for developing a new simulation processor, the “SP”. The SP is a system dedicated for simulation which performs parallel processing using up to 64 gate processors (GP). Using a newly devised pipeline control for each processor delivers high-speed and inexpensive simulation. By combining processors with a high-speed switch called ET, the degradation of processing speed due to the delay of information transmission in parallel processing can be prevented. The desired goal was achieved with the construction of the SP, a logic circuit with 4 million gates in which 32 Mbytes of memory could be simulated at high speed.

A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator

A method is presented to accelerate test generation, which synthesizes a test-generation circuit S(C, F) that combines the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test patterns are generated by searching the inputs to expose faults to the outputs using an ultrahigh-speed simulator (SP).<<ETX>>

Logic simulation system using simulation processor (SP)

A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a software system that optimizes hardware performance is discussed.<<ETX>>

Behavioral design and test assistance for pipelined processors

The authors propose a new concept in designing and testing processors. This approach generates behavioral-level test environments in VHDL for specific processor mechanisms, including automatic generations of test programs and behavioral descriptions. The authors have implemented an application to pipeline controllers.<<ETX>>

Automatic program generator for simulation-based processor verification

This paper presents an efficient test program generator for logic simulation that uses techniques developed for formal verification. Our test program generator enumerates all reachable states of a processor pipeline and generates instruction sequences for any reachable test case. The program covers all complicated test cases that are difficult to cover with random instructions and are impossible to cover by conventional test program generation methods.<<ETX>>

Performance evaluation of an event-driven logic simulation machine

The author evaluates the performance of an event-driven logic simulation machine, called the SP. Since an event-driven machine only schedules gates that have signal-changes on their inputs, it processes fewer gates than the level-sort machine does. However, if the event-driven machine spends too many clocks on dynamic scheduling, the simulation time cannot be reduced. The overhead for dynamic scheduling was measured, and it was found that it only averaged 2% over the total process. The evaluation was done by using the ISCAS89 benchmark circuits, and the results are shown on a machine cycle basis. Some special functions of the SP for acceleration were individually evaluated. The simulation speed was compared with that of a software simulator that used the same data structure and algorithm as the SP.<<ETX>>

Acceleration of behavioral simulation on simulation specific machines

Behavioral simulation is faster than gate-level logic simulation, however the simulation speed is too slow for large systems. Simulation specific machines accelerate simulation by parallel processing. We developed the method to extract parallelism from behavioral descriptions for fast simulation utilizing these machines. We evaluated our methods utilizing CAD accelerator TP5000. By the extraction of the parallelism the simulation speed is accelerated by about 7 times.