Ta-Chuan Liao

Novel Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels

The novel gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels (MNCs) have been, for the first time, fabricated using a simple process to demonstrate high-performance electrical characteristics and high immunity to short-channel effects (SCEs). The nanowire channel with high body-thickness-to-width ratio (TFin/WFin), which is approximately equal to one, was realized only with a sidewall-spacer formation. Moreover, the unique suspending MNCs were also achieved to build the GAA structure. The resultant GAA-MNC TFTs showed outstanding three-dimensional (3-D) gate controllability and excellent electrical characteristics, which revealed a high on/off current ratio ( > 108), a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering, as well as an excellent SCE suppression. Therefore, such high-performance GAA-MNC TFTs are very suitable for applications in system-on-panel and 3-D circuits.

A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure

A novel gate-all-around low-temperature poly-Si (LTPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster P/E speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.

Gate-All-Around Poly-Si TFTs With Single-Crystal-Like Nanowire Channels

The gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with single-crystal-like nanowire (NW) channels (SCLNCs) are demonstrated and characterized. Via the nanoscale nitride spacer, the Si NW can be easily transformed within one crystalline grain of the two-shot sequential-lateral-solidification poly-Si film. As compared with the planar ones, the GAA-SCLNC TFTs showed more excellent characteristics. The results clearly show that the variations of device characteristics can be reduced by increasing the numbers of NWs in the channels and an average mobility above 410 cm2/V·s with a low standard deviation can be achieved for the GAA-SCLNC TFTs with 20-NW channels.

High-Performance Single-Crystal-Like Nanowire Poly-Si TFTs With Spacer Patterning Technique

In this letter, high-performance single-crystal-like nanowire poly-Si TFTs with simple spacer patterning technique were demonstrated and characterized. Due to the nanoscale dimension formed by spacer patterning technique, each nanowire is easily transformed within one crystalline grain of the standard sequential-lateral-solidification (SLS) poly-Si film with the regularly arranged grains and thus performed with a single-crystal like device channel. Due to the high-crystallinity channel, together with the tri-gated structure, the fabricated devices revealed good device integrity of high field-effect mobility of 477 cm2/V · s and good ON/OFF current ratio of 1.07 × 108.

A Poly-Si Thin-Film Transistor with the In Situ Vacuum Gaps under the T-Shaped-Gated Electrode

A T-shaped-gated (T-gate) poly-Si thin-film transistor (TFT) with symmetric vacuum gaps has been proposed and fabricated simply with a selective-etching technique and an in situ vacuum encapsulation. The proposed TFT has demonstrated a higher maximum on-off current ratio and superior reliability compared to the conventional TFTs. This is attributed to the resulting offset region and vacuum gap to reduce the off-state leakage current and improve the hot-carrier reliability, while the extra subgate serves to induce an inversion layer at the offset region to maintain the on current during the on state. Therefore, such a T-gate poly-Si TFT is very suitable for manufacturing and applications in active-matrix flat panel electronics.

Reliability improvement of InGaZnO thin film transistors encapsulated under nitrogen ambient

The nitrogen ambient encapsulation (NAE) technique is introduced to improve the reliability issue for the amorphous InGaZnO (a-IGZO) thin-film transistors under positive gate bias stress (PGBS). For the NAE devices, the threshold voltage (Vth) shift is significantly decreased from 1.88 to 0.09 V and the reduction of saturation drain current is improved from 15.75 to 5.61 μA as compared to the bare a-IGZO counterparts after PGBS. These improvements are attributed to the suppression of negatively charged oxygen adsorption on the a-IGZO backsurface and thereby well maintain the channel potential of NAE devices, which in turn sustain the Vth during PGBS.

Gate-all-around polycrystalline-silicon thin-film transistors with self-aligned grain-growth nanowire channels

In this letter, gate-all-around (GAA) polycrystalline silicon thin-film transistors (TFTs) with self-aligned grain-growth channels were fabricated using excimer laser crystallization (ELC) on a recessed-nanowire (RN) structure. Via the RN structure constructed by a simple sidewall-spacer formation, location-controlled nucleation and volume-confined lateral grain growth within the RN body during ELC process have been demonstrated with only one perpendicular grain boundary in each nanowire channel. Because of the high-crystallinity channel together with GAA operation mode, the proposed GAA-RN TFTs show good device integrity of lower threshold voltage, steeper subthreshold slope, and higher field-effect mobility as compared with the conventional planar counterparts.

Novel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN–Alumina–Nitride–Vacuum–Silicon Structure

High-performance poly-Si-TFT-based TiN-alumina-nitride-vacuum-silicon (TANVAS) trapping-charge memory has been demonstrated utilizing high-k blocking oxide and vacuum tunneling layer for the first time. In particular, the vacuum, lowest k in nature, was introduced to replace the traditional tunneling oxide. Furthermore, the alumina high-k blocking oxide was applied to upgrade the electric field across the tunneling layer. Based on the enlarged k-value difference between the blocking and tunneling layers, the TANVAS featured considerable field enhancement across the tunneling layer, thus much improving the program/erase efficiencies. In addition, owing to the suppression of defect creation in the tunneling layer, the TANVAS also exhibited superior retention characteristics. These excellent memory characteristics of TANVAS are therefore promising for the 3-D Flash and system-on-panel applications.

Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory fabricated by a simple sidewall spacer formation

Abstract A novel omega-shaped-gated (Ω-Gate) poly-Si thin-film-transistor (TFT) silicon–oxide–nitride–oxide–silicon (SONOS) nonvolatile memory devices fabricated with a simple process have been proposed for the first time. The Ω-Gate structure inherently covered two sharp corners manufactured simply via a sidewall spacer formation. Due to the sharp corner geometry, the local electric fields across the tunneling oxide could be enhanced effectively, thus improving the memory performance. Based on this field enhanced scheme, the Ω-Gate TFT SONOS revealed excellent program/erase ( P / E ) efficiency and larger memory window as compared to the conventional planar (CP) counterparts. In addition, owing to the better gate controllability, the Ω-Gate TFT SONOS also exhibited superior transistor performance with a much higher on-current, smaller threshold voltage, and steeper subthreshold swing. Therefore, such an Ω-Gate TFT SONOS memory is very promising for the embedded flash on the system-on-panel applications.

Effect of Nitrogen Plasma Treatment on Electrical Characteristics for Pd Nanocrystals in Nonvolatile Memory

Pd nanocrystals (NCs) are successfully embedded in a TaN/SiO2/HfAlO/Si structure. The initial memory window increases at a higher rate with increasing fabrication temperature of Pd NCs compared with the linear variation of Pd NC density, which is related to the thermally induced neutral traps in the HfAlO film around Pd NCs. After manufacturing a TaN/SiO2/Pd NCs/HfAlO/Si/Al structure, the subsequent N2 plasma treatment is conducted at 300 °C for 3 min. The number of leakage current paths in the SiO2 blocking layer adjacent to TaN is clearly reduced, but that of leakage current paths in SiO2/HfAlO around Pd NCs is slightly increased owing to the thermal stress. The thermally induced neutral traps in the HfAlO film around the Pd NCs can be passivated by nitrogen atoms, which leads to the improvement of the final memory window for the Pd NC samples fabricated at 600–700 °C. However, the intrinsic traps in the HfAlO film play an important role in memory characteristic and the final memory window is reduced by thermal densification for the Pd NC samples fabricated at 500 °C.