Yoshihide Komatsu

A 125–1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain (Kv) and charge-pump (CP) current over C (ICP/C), the SSCG can realize not only adaptive bandwidth but also process independence at each operating frequency. The innovative point is the adaptive bandwidth control using Kv and ICP/C calibration. This control enabled a test chip to keep a sharp triangular SSC profile while operating over a wide frequency range (125 to 1250 MHz). The variations of VCO gain and CP current are reduced to one third those of the conventional architecture. At 1250 Mbps (625 MHz) the reduction of spectrum peak amplitude is 18.6 dB which is 2.3 dB better than the reduction obtained without calibration.

A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond

In this paper, we proposed a soft-error hardened latch (SEH-latch) scheme that has an error correction function in the fine process. To achieve this, we designed two types of SEH-latch circuits and a standard latch circuit using 130 nm 2-well, and also 90 nm 2-well CMOS processes. The proposed circuit demonstrated 2-order higher immunity through a radiation test using /spl alpha/-particles, and 1-order higher immunity through neutron irradiation.

Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias

We propose a method of reducing substrate noise and random fluctuations utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip that contained 10-M transistors for measuring random fluctuation tendencies. Under SA-FBB conditions, it reduced noise by 69.8% and reduced random fluctuations /spl sigma/(I/sub ds/) by 57.9%.

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond

Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset can-celing comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-μA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.

An ultra-wide range Bi-directional transceiver with adaptive power control using background replica VCO gain calibration

A novel transceiver with adaptive power control (APC) using a process and frequency monitor (PFM) based on a new adaptive power optimization concept is proposed. The PFM employs gain calibration with a replica VCO and operates in the background. A test chip, employing adaptive amplitude scaling (AAS), adaptive bias scaling (ABS), and adaptive supply-voltage scaling (AVS), achieved adaptive power over a wide frequency-range (0.05–3.4Gbps). At 100Mbps the measured power with APC was reduced by 75% compared to conventional architecture without APC.

Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias

This paper describes a method of reducing substrate noise and random variability utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip (130nm CMOS 3-well) that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip (90 nm CMOS 2-well) that contained 10-M transistors for measuring random variability tendencies. Under SA-FBB conditions, it reduced noise by 35.3-69.8% and reduced random variability σ(I ds ) by 23.2-57.9%.

An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration

A transceiver with adaptive power control using a process and frequency monitor (PFM) is proposed. The PFM employs gain calibration with a replica voltage-controlled oscillator (VCO) and operates in the background. A five-bit digital code detected by the VCO gain calibration is applied to an adaptive-amplitude driver, an adaptive-bandwidth receiver, and an adaptive-bandwidth phase-locked loop. A test chip was fabricated in a 110-nm CMOS process and achieved adaptive power control over a wide frequency range (0.05 to 3.4 Gb/s). At data rate of 100 Mb/s, the measured power consumption attained with adaptive power control was 75% lower than that attained with a conventional architecture without adaptive power control.

Transceiver Macro with Spread-Spectrum Clocking Capability for AC-Coupled Cable Interfaces

A transceiver macro for high-speed data transmission via cable in vehicles is proposed. The transceiver uses ac coupling and bidirectional interface topology for protecting LSIs against unexpected short of cable and harness/chassis and has a spread-spectrum-clocking (SSC) generator that reduces noise due to electromagnetic interference. A driver current control has been used for fast switching of data direction on accoupled interfaces. An adaptive bandwidth control has been used in a ΔΣ PLL to improve SCC significantly. A test chip has been fabricated and shows stable and bi-directional data communication with data rate of 162 to 972 Mbps through 20-m cable. Thanks to an optimum calibration of the SSC-PLL bandwidth, it reduces peak power at 33kHz by -23dB and provides 2% modulation at a data rate of 810Mbps.

Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond

This paper describes a soft error hardened latch (SEH-Latch) scheme that has an error correction function in the fine process. The storage node of the latch is separated into three electrodes and a soft error on one node is collected by the other two nodes despite the large amount and long-lasting influx of radiation-induced charges. To achieve this, we designed two types of SEH-Latch circuits and a standard latch circuit using 130-nm 2-well, 3-well, and also 90-nm 2-well CMOS processes. The proposed circuit demonstrated immunity that was two orders higher through an irradiation test using alpha-particles, and immunity that was one order higher through neutron irradiation. We also demonstrated forward body bias control, which improves alpha-ray immunity by 26% for a standard latch and achieves 44 times improvement in the proposed latch.