Tushar Gupta

High Level Power and Energy Exploration Using ArchC

With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. We propose a methodology using ArchC named Power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level power characterization at gate level. The requirements for power evaluation infrastructure are compatible processor models written in ArchC and RTL, and the Technology library. We show power results for a 32-bit MIPS processor with different benchmarks, based on 45nm technology.

RAAPS: Reliability Aware ArchC based Processor Simulator

In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstraction already have many ways to remove or handle soft errors. This paper aims at analyzing hard errors at functional level. We propose a methodology using state of the art failure models and simulators to provide the cumulative failure rate for a processor simulated at functional level.

Effects of various applications on relative lifetime of processor cores

The lifetime of integrated chip tends to decrease more and more with technology scaling. To check if a design is robust, in this paper we present RTME (Real Time MTTF Evaluation), a simulation framework that enables the evaluation of Reliability at higher level of abstraction layer. Using the output of RTME, we are able to distinguish the effect of different benchmarks on different blocks of the processor.