Olivier Héron

Defect analysis for delay-fault BIST in FPGAs

Detecting delay faults in SRAM-FPGAs can be done resorting to BIST. In this context, the objective of this paper is to analyse the timing behaviour of look-up tables (LUT) contained in FPGAs in both fault-free and delay faulty cases. We first show that the propagation delay of a LUT depends both on the transition pattern applied to its inputs and on the function implemented in it. This significant result questions the use of the basic assumption - the propagation delay of a LUT is independent of the function realized by it

High quality TPG for delay faults in look-up tables of FPGAs

considered in a number of recent papers. We next demonstrate that i) some physical defects in a LUT can change its propagation delay and ii) the delay due to a timing defect within the LUT varies depending on the location of the defect. We therefore conclude that unlike what is often done in existing FPGA BIST techniques, LUTs cannot be considered as programmable black boxes during test and testing their structure, either fully or partially, is needed to guarantee complete coverage of delay faults in the FPGA.

Analysis of on-line self-testing policies for real-time embedded multiprocessors in DSM technologies

The objective of this paper is to improve delay fault testing of SRAM-Based FPGAs. We have analyzed the physical behavior of resistive opens in a Look-Up Table (LUT) in previous papers and we have shown that i) these ones can change the propagation delay of the LUT and ii) the delay due to them varies depending on their size and their location. In this paper, we first show that resistive shorts are susceptible to make delay faults on the LUT output, leading to the same conclusions. As a result, we next show that the two-pattern pair and the implemented function of the LUT can significantly modify the sensitization of these defects, until making them non-observable on output. As a consequence, the basic properties for generating test vectors are not sufficient and new conditions are required to guarantee a most efficient delay test in a Manufactured-Oriented Test (MOT) context and in an Application-Oriented Test (AOT) context as well.

Impact of the application activity on intermittent faults in embedded systems

Advances in DSM technologies have a negative impact on yield and reliability of digital circuits. On-line self-testing is an interesting solution for detecting permanent and intermittent faults in non safety critical and real-time embedded multiprocessors. In this paper, we describe and evaluate three scheduling and allocation policies for on-line self-testing. We show that a policy that periodically applies a test procedure to the different processors in a way that considers idle times, test history of processors and task priorities offers a good trade-off between performance and fault detection probability.

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

Future embedded systems are going to be more sensitive to hardware faults. In particular, intermittent faults are going to appear faster in future technologies. Understanding the occurrence of faults and their impact on systems and applications can help to improve the fault-tolerance of systems. However, there is no study on their effects in more complex digital circuits. We propose an experimental platform for accelerating and catching the occurrence of intermittent faults in complex digital circuits. We experimentally show that intermittent faults can appear during the lifetime of the circuit, very early before the wear-out period. We studied the impact of processor activity on intermittent faults rate. We conclude that a continuous usage of circuits causes the occurrence of intermittent faults earlier than a low usage under identical operating conditions. We show that applications do not have the same sensitivity to intermittent faults.

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs

The objective of this paper is to propose a BIST scheme enabling the test of delay faults in all the Look-Up Tables (LUTs) of FPGA SRAMs, in a Manufacturing context. The BIST scheme does not consume any area overhead and can be removed from the device after the test thus, allowing the use of the whole circuit by the user. The structure we propose is composed of a simple test pattern generator, an error detector and a chain of LUTs. The chain of LUTs is formed alternatively by a LUT and a flip–flop. By using such a chain, the test of all delay faults in every LUT is enabled. In this paper, we develop an experiment based on the implantation of our BIST architecture in a Virtex FPGA from Xilinx. The purpose of this experiment is to show the feasibility of our solution. As a result, one important issue from this solution is its ability to detect the “smallest” delay faults in the LUTs, i.e. the smallest delays that can be observed on a LUT output.

BIST of delay faults in the logic architecture of symmetrical FPGAs

The objective of this paper is to propose a method to test all the delay faults located in Look-Up-Tables (LUTs) of SRAM-based symmetrical FPGAs. This method is developed in a Manufacturing-Oriented Context (MOT). In the first part of the paper, the timing behavior of the LUTs and the physical defects inducing delay faults in the LUTs are analyzed. Then, the detection conditions to test such delay faults are established and requirements on test vectors are derived. Finally a test configuration scheme and its associated test sequence able to test exhaustively the delay faults in all LUTs of a symmetrical FPGA are proposed.

Relation between HCI-induced performance degradation and applications in a RISC processor

In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic architecture of symmetrical FPGAs. This scheme is applicable in a manufacturing-oriented test (MOT) context. Our technique enables the detection of delay faults in the logic architecture and consists in chaining the logic cells in a specific way. The test of all the delay faults can be done with a reduced test sequence and does not require expensive ATE. To illustrate its feasibility, this BIST approach has been implemented in a VIRTEX FPGA from XILINX Inc.

High Level Power and Energy Exploration Using ArchC

Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter hot carrier injections (HCI). This failure mechanism causes a performance degradation of digital ICs. The evaluation of timing degradations becomes a must-have to ensure the expected time-to-market and IC lifetime early in the design flow. In this paper, we present a design/verification flow at front-end from which we accurately analyze the impact of instruction-set architecture on processor timings. We show results on a RISC processor named AntX and designed in a 40 nm TSMC technology. Using typical-case scenarios can increase the maximum operating frequency by 15% on average compared to a worst-case scenario, while considering the same lifetime. We also identify that the shift operations cause the highest timing degradations along the long processor paths.

Requirements for delay testing of look-up tables in SRAM-based FPGAs

With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. We propose a methodology using ArchC named Power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level power characterization at gate level. The requirements for power evaluation infrastructure are compatible processor models written in ArchC and RTL, and the Technology library. We show power results for a 32-bit MIPS processor with different benchmarks, based on 45nm technology.