Tyler A. Lowrey

Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process

Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology

Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography

Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories

Method to form self-aligned gate structures and focus rings

Spacers for field emission display fabricated via self-aligned high energy ablation

Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors

Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM

Method to form high aspect ratio supports (spacers) for field emission display using micro-saw technology

ARRAY OF READ-ONLY MEMORY CELLS, EACCH OF WHICH HAS A ONE-TIME, VOLTAGE-PROGRAMMABLE ANTIFUSE ELEMENT CONSTRUCTED WITHIN A TRENCH SHARED BY A PAIR OF CELLS