Tzong-Sheng Chang

Ultra high density 3D via RRAM in pure 28nm CMOS process

In this paper, we present an ultra high density 3D Via RRAM with 28nm HKMG CMOS fully compatible process. It is the first time to report a cross-point 3D RRAM formed by the stacked 30nm × 30nm Cu Via and Cu metal line of 28nm HKMG CMOS Cu single damascene process. The 3D Via RRAM cell consists of a TaON-based resistive film, Cu Via as top electrode, and Cu metal as bottom electrode. The TaON-based RRAM film is a composite layer of backend metal glue layer of Ta and TaN in 28nm Cu damascene process. Moreover, in the compact 3D Via RRAM structure, the unit area of a single stacked cell-string is reduced to only 4 times of Via size by 28nm CMOS design rules. Since the cross-point 3D Via RRAM is fabricated without extra TMO film or process step, this excellent cell scalability and compatibility can provide a competitive low cost and high density embedded NVM solution in advanced CMOS logic nodes.

Development of a Magnetic Cusp Gun for Terahertz Harmonic Gyrodevices

A magnetic cusp gun (MCG) is being developed to generate an axis-encircling electron beam, which is called the large orbit beam, which is going to drive a 0.396-THz fourth-harmonic gyrotron. Developing an MCG imposes crucial challenges on a simultaneously minimizing guiding center deviation and velocity spread of the electron beam, particularly because an ultrahigh magnetic compression ratio is unavoidable, as is the case for a terahertz (THz) gyrotron. The study of the electron dynamics in the MCG reveals that, close to the emitter, a pair of focusing electrodes are employed to construct a special focusing and accelerating electric field as a way to balance the space-charge influence and guiding center deviation. Investigation indicates that both the electron-beam generalized-angular-momentum spread and the guiding center distribution are the critical factors contributing to beam parameter spread. Intensive optimization generates a high-power MCG with a pitch factor of 1.5, the highest magnetic field of 4 T, minimum transverse velocity spread of 1.1%, and a beam current of 2 A. The key parameters exhibit excellent stability tuning over a wide range of beam current and magnetic field. These merits enable the harmonic gyrotrons or even the frequency-tunable THz gyrotrons to be developed.

Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process

A self-rectifying twin-bit RRAM in a novel 3D interweaved cross-point array has been proposed and demonstrated in 28nm CMOS BEOL process. With TaOx RRAMs on both sides of a single Via, the twin-bit RRAM cell is composed by Cu back-end layers only. Excellent selectivity by its asymmetric IV characteristic enables the twin-bit 1R cells to be efficiently stacked in 3D cross-point arrays.

A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process

A new and compact high-k dielectric breakdown one-time programmable (OTP) cell in pure 28-nm high-k metal gate (HKMG) process is proposed. By adopting a self-aligned twin-gate isolation (TGI) made by merged gate spacer, the new OTP cell can operate independently with a very small cell area. Fabricated by a pure 28-nm HKMG CMOS logic process, this OTP cell successfully achieves an ultrasmall cell size of 0.0441 μm2 on 28-nm HKMG CMOS logic platform. Using high-k dielectric breakdown as its program mechanism, the antifuse TGI OTP memory has more than three orders of ON/OFF read window with a low program voltage of 4 V in 20 μs. Furthermore, a highly density 64-kbit TGI OTP array has been fabricated and successfully demonstrates the new superior isolation and reliability performances.

Characterization of Multilayer Metal Gate Fuse in 28-nm CMOS Logic Technology

In this letter, the characteristics of metal gate (MG) fuses in 28-nm complementary metal-oxide-semiconductor (CMOS) technology are investigated. Through analyzing its initial and after program characteristics, the fuse burning process is studied. The stacked layer MG fuses exhibit two stages in the burning process. These unique programming characteristics of the MG electronic fuse provide insights for the future development low power and high reliable electrically programmable fuses by advanced nanoscale CMOS technologies.

Modal analysis and efficient coupling of TE₀₁ mode in small-core THz Bragg fibers.

We report a design of low-loss THz Bragg fibers with a core size on the order of wavelength that operates near the cutoff frequency of its TE01 mode. We also propose a broadband Y-type mode converter based on branched rectangular metallic waveguides to facilitate coupling between the TE01 mode of the Bragg fiber and the TEM mode in free space with 60% efficiency. Our fiber holds strong promise to facilitate beam-wave interaction in gyrotron for high-efficiency THz generation.

Via Diode in Cu Backend Process for 3D Cross-Point RRAM Arrays

In this paper, a fully logic compatible via diode is developed for high-density resistive random access memory (RRAM) array applications. This novel via diode is realized by advanced 28nm CMOS technology with Cu damascene via. The device is stacked between a top Cu via and a bottom Cu metal with a composite layer of TaN/TaON based dielectric film. An asymmetric current-voltage characteristic in this MIM structure provides a forward/reverse current ratio up to 106. In a cross-point RRAM array, the suppression of sneak current path by incorporating this via diode enables array size to be greatly expended. Via diode provides an excellent solution for high-density embedded nonvolatile memory applications in the nano-scale CMOS technology.

High-Density FinFET One-Time Programmable Memory Cell With Intra-Fin-Cell-Isolation Technology

The one-time programmable (OTP) cell with intra-Fin-cell-isolation (IFCI) on the FinFET high-k metal gate (HKMG) CMOS process is proposed and demonstrated. The field-enhanced dielectric breakdown at Fin corners enables this OTP cell to be operated at low program voltage with fast program speed. The new intra-Fin cell-to-cell isolation eliminates the required wide spacing in the conventional isolation schemes, which successfully shields the neighboring cells from program and read disturbs. Without introducing extra masks or process steps, the CMOS compatible IFCI OTP cell achieves an ultrasmall cell size of 0.076 μm2. More than six orders of ON-/OFF-read window is achieved under 4 V programming within 20 μs.

A new saw-like self-recovery of interface states in nitride-based memory cell

A new saw-like self-recovery Self-Aligned Nitride (SAN) memory cell is proposed and fabricated in 28nm high-k metal gate (HKMG) CMOS process for high-density logic NVM applications. The cell is operated with Source-Side Injection (SSI) for programming and band-to-band hot holes (BBHH) for erasing. Two effective self-heating recovery mechanisms are proposed and performed to maintain a stable On/Off read window after cycling stresses. Besides, the characteristic and reliability comparison of the SAN cell in other technology nodes, 90nm/45nm/32nm, are characterized to further verify the saw-like self-detrapping and self-recovery operation. The new 28nm HKMG SAN memory cell with the self-detrapping recovery results excellent and superior endurance performance and can provide a very promising solution for logic NVM in advanced technologies.

Self-Rectifying Twin-Bit RRAM in 3-D Interweaved Cross-Point Array

A new self-rectifying twin-bit RRAM in a novel 3-D interweaved cross-point array has been proposed and demonstrated in 28-nm high-k metal gate CMOS back end of line (BEOL) process. This high density of array architecture with the cell size only 70 × 100 × 187 nm can be manufactured without additional mask or process. The RRAM film is formed by via plug over shifting between two metal lines in back-end process with TaN/TaOxN RRAMs on both sides of a single via. The BEOL RRAM shows large read window between states. Fast switching time of 1 us for set operation and 10 us for reset was demonstrated. Excellent selectivity by its asymmetric IV characteristic enables the twin-bit 1R cells to be efficiently stacked in 3-D cross-point arrays without select transistors.