Kuang-Hsin Chen

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

A 7nm CMOS platform technology featuring 4 th generation FinFET transistors with a 0.027um 2 high density 6-T SRAM cell for mobile SoC applications

For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V. The 4th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.

A high-performance, high-density 28nm eDRAM technology with high-K/metal-gate

This paper presents industrys smallest 0.035um2 high performance embedded DRAM cell with cylinder-type Metal-Insulator-Metal (MIM) capacitor and integrated into 28nm High-K Metal Gate (HKMG) logic technology. This eDRAM memory features an HKMG CMOS compatible (low-thermal low-charging process) high-K MIM capacitor with extreme low leakage (<0.1fA/cell). Access transistor with HKMG shows excellent driving capability (>50uA/cell) with <1fA/cell leakage in 28nm cell and <3fA/cell in 20nm cell (0.021um2). We demonstrate first functional silicon success of 28nm eDRAM macro. 600/550 MHz operating frequency is achieved at typical/worse cases.

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

A high density cylinder-type MIM capacitor integrated with advanced 28nm logic High-K/Metal-Gate process for embedded DRAM

A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve sufficient storage capacitance without significantly impacting logic transistors. This paper describes techniques to achieve cylinder-type MIM capacitors capacitance >;10fF/cell and keep the low leakage (<;0.1fA/cell) requirements. The MIM dielectric reliability test passes Time Dependent Dielectric Breakdown (TDDB) lifetime (>;10 years). The test vehicle is composed of 72 macros of 4.5Mb each. We successfully demonstrate fully functional good yield of 28nm eDRAM 324Mb test vehicle with access speed >;330MHz.

Modeling isolation-induced mechanical stress effect on SOI MOS devices

In this paper, the mechanical stress effect of SOI MOS devices was analysed. The width dependence of stress effect and drain current shift were evaluated.