Udo Wille

S/390 parallel enterprise server generation 3: a balanced system and cache structure

Since initiating the information technology industry-wide transition from bipolar to CMOS technology with the first generation of S/390® processors in 1994, IBM reached another major milestone with the introduction of the third generation in September 1996. The balanced system and cache structure and the modularity of the components of Generation 3 support a wide performance range from a uniprocessor to a high-performance multiprocessing system. Because of this modularity, Generation 4 is also based on this structure.

A CMOS implementation of the ESA/390 mainframe architecture

Abstract The ESA/390 high-end CISC architecture has been implemented using a 1.0 um CMOS standard cell technology. The resulting 4 chip, 2.5 Mio, transistor microprocessor is used in IBMs 9221 line of midrange systems. This paper gives an overview of the technology used and a description of the implementation. The dataflow and pipelining scheme are described. Instructions of low complexity are executed RISC-like in a single cycle under full hardware-control, while complete-instructions are interpreted by microcode.

Level-2 cache for high performance /390 μ-processors

Abstract A L2 cache chip design for high performance /390 μ-processors in a multiprocessor environment is presented. Design objectives, logic and technological implementation as well as measured results are discussed. The design features a 96 k Bytes L2 cache-, its associated directory- and LRU arrays, dataflow and control logic integrated on one CMOS standard cell chip with more than 6 million transistors. Its nominal operating frequency is 75 Mhz. 16 bytes wide memory and PU busses are serviced by operating two L2-cache chips in parallel.