Won-Sok Lee

A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC and AC performances of Si NW MOSFETs on NW diameter (DNW) and gate oxide thickness has been investigated. A Si NW device with the scaled DNW of 9 nm and thin equivalent oxide thickness (EOT) of 0.9 nm improved both on-current and electrostatic characteristics. Finally, a Nanowire-On-Insulator (NOI) structure has been proposed to enhance the AC performance of a multiple-stacked NWs structure, which improves DC performance but has the issue of high parasitic capacitance. As a result, the simulated AC performance of a triple-NOI structure was improved by around 20% compared to conventional triple NW structure.

In 0.53 Ga 0.47 As-Based nMOSFET Design for Low Standby Power Applications

III-V n-channel MOSFETs based on InxGa1-xAs are evaluated for low-power (LP) technology at a sub-10-nm technology node. Aggressive design rules are followed, while industry-relevant FinFET architecture is selected. We show, for the first time, quantum confinement-related leakage and performance tradeoff done self-consistently in performance evaluation using an in-house developed semiclassical tool. In this paper, we focus on In0.53Ga0.47As as the channel material, as it has been investigated heavily in the literature. Furthermore, it has a bulk bandgap EG similar to that of Ge, another highly studied complementary p-FET channel material. Higher In-content results in lower EG and hence larger band-to-band tunneling (BTBT) current, resulting in more stringent design requirements for LP applications. A comparison is done with the state-of-the-art tensile-Si (t-Si) technology, with roughly 2-GPa stress, under similar constraints LG, design rules). Thus, we show that while for 0.75 V operation, In0.53Ga0.47 As performance is limited by the BTBT and fails to outperform t-Si, it starts to perform better than t-Si below 0.7 V. VDD scaling further results in an increased performance gap between the two material systems.

3-Dimensional Analysis on the GIDL Current of Body-tied Triple Gate FinFET

Triple gate FinFET is emerging as a promising candidate for the future CMOS device structures because of its immunity to short-channel effect. However, the suppression of GIDL is a significant challenge for its application. In this paper, we discuss the characteristics of GIDL on FinFET and extensively analyze the influence of the device technology on GIDL. The analysis is expected to give guidelines to the future development of triple gate FinFET

A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology

for 4F2 DRAM Cell Array with sub 40 nm Technology Jae-Man Yoon, Kangyoon Lee, Seung-Bae Park, Seong-Goo Kim, Hyoung-Won Seo, Young-Woong Son, Bong-Soo Kim, Hyun-Woo Chung, Choong-Ho Lee*, Won-Sok Lee* *, Dong-Chan Kim* * *, Donggun Park*, Wonshik Lee and Byung-Il Ryu ATD Team, Device Research Team*, CAEP*, PD Team***, Semiconductor R&D Division, Samsung Electronics Co., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do, 449-711, Korea Tel) 82-31-209-4741, Fax) 82-31-209-3274, E-mail)

Impact of BTBT, stress and interface charge on optimum Ge in SiGe pMOS for low power applications

The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (IEFF @ fixed IOFF) standpoint is evaluated, considering three key device aspects - stress, band-to-band-tunneling (BTBT), and interface charge density (DIT). The analysis reveals that while for high Ge (>90%), performance is limited by BTBT, overall stress reduction beyond Ge 65% further limits performance. Including realistic (DIT) profile further shows that optimum Ge content is between 40%~50% for low power applications.

Influence of Preferred Gate Metal Grain Orientation on Tunneling FETs

The novel effects of preferred gate metal grain orientation on tunneling FETs (TFETs) have been investigated for the first time. It has been observed that TFETs have preferred gate metal grain orientation to lower work-function variation (WFV) unlike MOSFETs. In the case of TFETs, when the metal gate grain orientation with low work function is dominant, the WFV is effectively suppressed. This brief provides a design guideline for the suppression of TFET WFV.

Investigation of Body Bias Dependence of Gate-Induced Drain Leakage Current for Body-Tied Fin Field Effect Transistor

The body bias dependence of gate-induced drain leakage (GIDL) current for a fin field effect transistor fabricated on a bulk Si wafer (bulk FinFET) is investigated. The local damascene (LD) bulk FinFET is measured under various bias conditions and the effect of the body-bias-induced lateral electric field on GIDL current is evaluated. A lateral electric field shield effect under fin depleted condition is proposed and it is validated by the three-terminal band-to-band tunneling current model. The GIDL current of the bulk FinFET can be reduced by reducing the body bias, and an improvement in retention characteristics is expected.

TCAD for Next Generation Technology and Product Development

As the lithography-driven scaling has been replaced by physically-based scaling, TCAD has become a principal tool for virtual characterization of technology development. This paper describes roles, benefits, capabilities and perspectives of TCAD applications for technology and product development. Emerging challenges in the nanotechnology era are also discussed