Ujwal Radhakrishna

Physics-based GaN HEMT transport and charge model: Experimental verification and performance projection

A physics-based compact transport and charge model for GaN HEMTs has been developed. The model includes effects such as self-heating, non-linear access region behavior, electron-phonon interaction etc. The model is validated against fabricated devices and is used to evaluate fT improvements in short channel devices. The model is also a suitable base for GaN FET circuit simulation compact models.

Modeling of SOI-LDMOS Transistor Including Impact Ionization, Snapback, and Self-Heating

A physics-based compact model for silicon-on-insulator lateral double-diffused metal-oxide-semiconductor transistors including impact ionization, subsequent snapback (SB), and self-heating (SH) is presented. It is observed that the SB effect is caused by the turn-on of the associated parasitic bipolar transistor. The model includes the effect of device SH using resistive thermal networks for each region. Comparisons of modeling results with device simulation data show that, over a wide range of bias voltages, the model exhibits excellent accuracy without any convergence problem.

Negative Capacitance Behavior in a Leaky Ferroelectric

We present a simulation study of the negative capacitance effect incorporating leakage through the ferroelectric (FE) negative capacitor. The dynamics of the FE is modeled using the Landau-Khalatnikov equation. When an FE and a dielectric are simply connected in series without a metal contact between them, the stabilization of negative capacitance remains unchanged irrespective of leakage. However, when a metal is used, any finite leakage through the FE makes it impossible to stabilize negative capacitance at the steady state. Nonetheless, when a voltage is applied, the series configuration enters the negative capacitance state and as long as the gate voltage is cycled faster than the time needed by the leakage current to discharge all the capacitors, the transistor shows improved subthreshold swing. These results are expected to provide insight into understanding and analyzing recent experimental results on negative capacitance.

A 5.9-GHz Fully Integrated GaN Frontend Design With Physics-Based RF Compact Model

This paper presents the design of a fully integrated high-efficiency and high-power RF frontend for the IEEE 802.11p standard in GaN HEMT technology. An embedded transmitter/receiver (Tx/Rx) switching scheme and a dual-bias power amplifier linearization technique are used to improve Tx efficiency and linearity. An accurate physics-based nonlinear large-signal device model is developed and used for the design, providing insight into the impact of the behavioral nuances of the GaN HEMTs on RF circuit performance. The fully integrated RF frontend is fabricated in 0.25- μm GaN-on-SiC technology and occupies only 2 mm × 1.2 mm. The Tx branch achieves 48.5% drain efficiency at 33.9 dBm, Psat with 28-V supply. With orthogonal frequency-division multiplexing modulated signals, it achieves 30% average efficiency at 27.8-dBm output power while meeting the -25-dB error vector magnitude limit without predistortion. The Rx branch achieves +22-dBm output third-order intercept point with 3.7-dB noise figure at 12-V supply. The fully integrated high-efficiency and linear RF frontend designed with physics-based RF GaN compact models is demonstrated for the first time for future device-to-device applications.

Quantifying the impact of gate efficiency on switching steepness of quantum-well tunnel-FETs: Experiments, modeling, and design guidelines

DC and RF characterization up to 10 GHz from RT to T = 77 K combined with detailed modeling are used for the first time in a comprehensive investigation of the impact of gate efficiency on the subthreshold swing (SS) in Quantum-well Tunnel-FETs (QWTFETs). Calibrated modeling of experimental InGaAs/GaAsSb QWTFETs based on IV, CV and RF measurements and full quantum-mechanical (QM) simulations suggest that only 55% of the gate voltage contributes to the tunneling current modulation which results in degraded switching steepness. This is due to the coupling of the tunneling junction with the MOS structure, that severely degrades the gate efficiency. The proposed model can be adapted to analyze the gate efficiency in various TFET designs, and/or to use in circuit simulation. Based on the QM simulations, design guidelines resulting in up to 1.4X improved gate efficiency to ~78% in our device structure are proposed.

Work Function Engineering for Performance Improvement in Leaky Negative Capacitance FETs

We analyze the effects of ferroelectric leakage on the performance of a negative capacitance field-effect transistor (NCFET), which has an intermediatemetallic layer between the ferroelectric and the high-K dielectric. We show that, when designed without taking the dielectric leakage into account, the NCFET performance can actually degrade significantlywith respect to that of the baseline FET. To overcome these detrimental effects of leakage, we propose the concept of work-function engineering, where metals of dissimilar work-functions are used for the external gate electrode and the intermediate metallic layer. Using this approach, the ferroelectric charge–voltage characteristic is shifted along the voltage axis, which results in superior performance of the NCFET.

A Fully Integrated Inductor-Based GaN Boost Converter With Self-Generated Switching Signal for Vehicular Applications

An inductor-based GaN dc-boost converter with self-generated switching signal is proposed to remove power and area consuming gate drivers for toggling a large transistor switch. All the active and passive components are integrated on a 3 mm ×3 mm die using 0.25-μm GaN-on-SiC process. The circuit operates at 680-MHz switching frequency with 0.24 W/mm2 power density at 20-V output voltage for vehicular applications with 12-V car battery input.

MIT virtual source GaNFET-RF compact model for GaN HEMTs: From device physics to RF frontend circuit design and validation

A physics-based compact transport and charge model for RF-GaN HEMTs has been developed, including device self-heating, non-linear access region behavior, noise, etc. The model is validated against measurements from device-level DC up to circuit-level. The model is implemented in Verilog-A that is a suitable base for circuit simulations.

GaNFET compact model for linking device physics, high voltage circuit design and technology optimization

This work is the first demonstration of a physics-based GaN HEMT compact model that is calibrated and verified all the way from individual device-to a HV-buck converter circuit, along with an illustration of use in technology optimization. GaN HEMT based high voltage (HV) switching converters are gaining foothold in the medium voltage (<;1000 V) power conversion applications. The superior breakdown voltage, operating frequency, and high temperature performance of GaN HEMTs enable improved conversion efficiency and smaller footprint of the converters [1]. In order to design such high voltage GaN circuits, the device compact model must accurately describe static and dynamic switching behavior to enable designers to gain insight into the impact of the behavioral nuances of the GaN HEMTs on HV circuit performance, such as non-quasi-statics, which is not possible with the available models such as EEHEMT, Curtice, and Angelov models [2]. The model is validated against DC-IV, -CV, and pulsed-IV measurements of fabricated devices and is then verified by comparing measured and simulated signals in a commercial buck converter. Furthermore we demonstrate that our physics-based model can be used as a device design and multi-dimensional optimization tool to estimate device parameters such as field plate (FP) lengths and FP dielectric thicknesses (td) to maximize the switching figure-of-merit (FoM), BV/RonQg.

High-yield large area MoS 2 technology: Material, device and circuits co-optimization

Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to the ultrathin nature, good transport properties and stable crystalline structure of MoS2. However, the reported devices and circuits based on this material have low yield because of various variation sources inherent to the growth and fabrication technology. In this work, we develop a variation-aware design flow and yield model to evaluate the MoS2 technology and provide a guideline for the co-optimization of the material, devices and circuits. Test chips with various inverters and basic logic gates (such as NAND and XOR) are fabricated as demonstration of the close-to-unit yield of the proposed technology platform.