Ulf R. Hanebutte

RAPL: memory power estimation and capping

The drive for higher performance and energy efficiency in data-centers has influenced trends toward increased power and cooling requirements in the facilities. Since enterprise servers rarely operate at their peak capacity, efficient power capping is deemed as a critical component of modern enterprise computing environments. In this paper we propose a new power measurement and power limiting architecture for main memory. Specifically, we describe a new approach for measuring memory power and demonstrate its applicability to a novel power limiting algorithm. We implement and evaluate our approach in the modern servers and show that we achieve up to 40% lower performance impact when compared to the state-of-art baseline across the power limiting range.

Memory power management via dynamic voltage/frequency scaling

Energy efficiency and energy-proportional computing have become a central focus in enterprise server architecture. As thermal and electrical constraints limit system power, and datacenter operators become more conscious of energy costs, energy efficiency becomes important across the whole system. There are many proposals to scale energy at the datacenter and server level. However, one significant component of server power, the memory system, remains largely unaddressed. We propose memory dynamic volt age/frequency scaling (DVFS) to address this problem, and evaluate a simple algorithm in a real system. As we show, in a typical server platform, memory consumes 19% of system power on average while running SPEC CPU2006 workloads. While increasing core counts demand more bandwidth and drive the memory frequency upward, many workloads require much less than peak bandwidth. These workloads suffer minimal performance impact when memory frequency is reduced. When frequency reduces, voltage can be reduced as well. We demonstrate a large opportunity for memory power reduction with a simple control algorithm that adjusts memory voltage and frequency based on memory bandwidth utilization. We evaluate memory DVFS in a real system, emulating reduced memory frequency by altering timing registers and using an analytical model to compute power reduction. With an average of 0.17% slowdown, we show 10.4% average (20.5% max) memory power reduction, yielding 2.4% average (5.2% max) whole-system energy improvement.

Improving user comfort and office energy efficiency with POEM (personal office energy monitor)

Consensus exists in much of industry and academia that engaging end-users is an essential element for improving energy efficiency in office buildings. We present our experiences implementing and deploying POEM (Personal Office Energy Monitor) with real office users. POEM is an end-user eco-feedback application. It provides detailed personalized data on energy usage and ambient conditions to each office user, as well as reporting aggregates for building-level management and policy setting. The POEM UI also allows users to state their subjective feeling of comfort. The system aggregates those inputs and informs the building manager to take corrective action if needed - thus closing the control loop between the people and the building. We report our findings from pilot tests of POEM prototype.

ISx: A Scalable Integer Sort for Co-design in the Exascale Era

This paper introduces a new scalable integer sort application inspired by the NAS Parallel Benchmark integer sort. We provide a detailed analysis of the NPB integer sort to motivate the development of ISx-a new integer sort for co-design. ISx is a highly modular application implemented in the OpenSHMEM parallel programming model and supports both strong and weak scaling studies.

Multi-Threaded OpenSHMEM: A Bad Idea?

The purpose of this document is to stimulate discussions on support for multi-threaded execution in OpenSHMEM. Why is there a need for any thread support at all for an API that follows a shared global address space paradigm? In our ongoing work, we investigate opportunities and challenges introduced through multi-threading, namely implementation challenges and opportunities and required -- as well desirable -- extensions to the API.

A novel approach to memory power estimation using machine learning

Reducing power consumption has become a priority in microprocessor design as more devices become mobile and as the density and speed of components lead to power dissipation issues. Power allocation strategies for individual components within a chip are being researched to determine optimal configurations to balance power and performance. Modelling and estimation tools are necessary in order to understand the behaviour of energy consumption in a run time environment. This paper discusses a novel approach to power metering by estimating it using a set of observed variables that share a linear or non-linear correlation to the power consumption. The machine learning approaches exploit the statistical relationship among potential variables and power consumption. We show that Support Vector Machine regression (SVR), Genetic Algorithms (GA) and Neural Networks (NN) can all be used to cheaply and easily predict memory power usage based on these observed variables.