Unai Alvarado

Energy harvesting technologies for low-power electronics

Power consumption is one of the most critical issues when designing low-cost electronic devices, such as sensing nodes in wireless sensor networks. To support their operation, such systems usually contain a battery; however, when the battery has consumed all its energy, the node (e.g. the sensor) must be retrieved and the battery replaced. If the node is located in a remote and non-accessible placement, battery replacement can become an expensive (and even impossible) task. This way, energy harvesting has emerged as a suitable alternative to supply low-power electronic systems, by converting ambient energy into electric power. Scavenged energy can be used to directly supply the circuits, or stored to be used when needed. This paper summarises the power needs of a general wireless sensor node and describes the main principles of most representative energy harvesting technologies. Copyright

Low power RF circuit design in standard CMOS technology

Introduction.- Power Considerations in Analog Rf CMOS Circuits.- Impact of Architecture Selection on RF Front-End Power Consumption.- Technology Structural Alternatives in Standard CMOS Technologies for Low-Power Analog Design.- Schematic Design Techniques for Power Saving in RF.- RF Amplifier Design.- Mixer Design.- Phase Locked Loop (PLL) Design.

Design for test of a low power multi-standard GPS/GALILEO RF front-end

This contribution deals with the complete design of a multi-standard GPS/GALILEO front-end, from setting the specifications through to the complete characterization of the device. Special focus will be given to the design for test and the characterization of the design, as optimizing the time spent on this improves time-to-market for the product under development. The highly integrated, low power GPS/GALILEO front-end is designed with a low-IF architecture. The front-end exhibits a voltage gain of 103dB with a power consumption of 66mW from a 3V voltage supply and 38mW if the internal dual-gain LNA is switched OFF. The SSB noise figure of 3.7dB which makes it suitable for high sensitivity applications. Te implemented architecture allows 3 different configurations, adding flexibility to its future applications.

GNSS Complementary Positioning System performance in railway domain

An on-board Complementary Positioning System (CPS) has been proposed to overcome the limitation of GNSS positioning systems. This paper deals with the test phase of CPS to guarantee the localization functions in areas in which GNSS signals are not available. In order to analyze the suitability of CPS its performance in a railway operational line has been evaluated. The CPS is based mainly on GNSS, Inertial Measurement Units (IMU) and Wireless Communications Technologies (WCT) as input sources for localization. The field tests have been carried out in an operational regional line and availability has been increased as it was the purpose.

A CMOS sensor signal conditioner for an automotive pressure sensor based on a piezo-resistive bridge transducer

This paper describes the design of a Sensor Signal Conditioner for a pressure sensor transducer in automotive applications. The circuit has been implemented in a 0.35 um CMOS process and comprises an Instrumentation Amplifier (IA), a 2nd order Chebyshev active low pass filter and an 1st order incremental ADC. The IA consumes 3mA with a supply voltage of 5V. Measured gain is 30 dB with 10° of phase margin. The PSRR and CMRR are 60 dB and 90 dB, respectively. Measured input referred offset voltage is 22 uV. The IA shows good linearity up to an amplitude of 2.5 Vpp at the output. With this output swing of 2.5 Vpp harmonics are 60dBc for a 1 KHz input tone. The PSD of the input referred noise is below 150 nV/VHz. The ADC current consumption of the ADC is 1.3 mA at 400 S/s. Its INL ±2.5 LSB for a 13 bit resolution, which gives an ENOB of 11.4 bits. Input referred noise results in 0.85 LSB or an ENOB of 11.4 bits. The IA combined with the ADC has an overall area of 0.71 mm2. Its INL of ±4 LSB. Again, the input referred noise is in 0.85 LSB or 11.5 bits.

Challenge oriented methodology for analog integrated circuit layout design training

This paper presents the course of Electronic Design offered by Tecnun (University of Navarra) in the Electronic Communication Engineering degree. The aim of this course is to bring the student closer to the professional integrated circuit layout world and it is oriented towards a final design challenge in which the students compete between them to obtain the maximum grade. Five modules with theory and lab work and the final project or challenge compose the course. Each module is focused on a certain component fabrication and solves a specific layout issue in the theory section. On the other hand, the practical work gains complexity progressively so the students can face the final challenge with guarantees. Once the challenge is completed, each student must present the design flow and the obtained results to the rest of the class and to a special panel of professional designers. During these presentations, the designs are evaluated from an industrial point of view. The implementation of this methodology has demonstrated that challenge orientated training improves the students interest in the course, their technical communication skills and prepares them for professional analog design scenarios.

A low power CMOS temperature-to-frequency converter for RFID applications

This paper presents the design of a low power temperature sensor based on temperature-to-frequency conversion for RFID applications. The variation of temperature is detected by a PTC resistor that determines the reference current of a bootstrapped cascode source. This current is used to bias an active inductor. The self-resonance frequency varies accordingly to the shift of the current, thus providing the temperature to frequency conversion. The circuit has been implemented using a standard 65 nm CMOS technology. A frequency of oscillation of 31.3 MHz at 20°C has been obtained, with an estimated sensitivity of 50.5 kHz/°C, a resolution of 0.12°C and a power consumption of 21.8 uW within the 0-80°C temperature range.

RF Amplifier Design

This chapter deals with the design of the basic amplifying stages. It also provides the introductory tools required for the design of any kind of amplifier (VGA, LNA, BUFFERS, etc). Due to its importance for CMOS ICs, the low noise amplifier is deeply studiedi this chapter.

Power Considerations in Analog RF CMOS Circuits

This chapter deals with the basic principles of power consumption in RF CMOS analog circuits. These concepts are used extensively throughout the book; therefore the different sections of the chapter are dedicated to the presentation of general definitions and formulas. Section 2.1 introduces the different sources of power dissipation in analogue circuits, regarding both static and dynamic power dissipation mechanisms, from a steady and transient perspective respectively. Section 2.2 reviews the classical considerations for low power digital circuits and their structures. Then, section 2.3 deals with the power supply scaling as a means to achieve low- power benefits, which is highly related to section 2.2, and finally section 2.3 outlines the practical limits in power consumption from a triple perspective: starting from the front-end architecture and CMOS technology constraints through the RF and analog circuits.

Phase Locked Loop (PLL) Design

The last building block covered in the book is the Phase Locked Loop (PLL), virtually used in every integrated communication front-end. The complexity of this system is high; therefore the first section is dedicated to the basic concepts related to both PLL system architectures and basic components. The architecture of the classical phase locked loops used in RF IC designs are presented in that first section. Nevertheless, from the power consumption point of view, the decision on the architecture of the whole PLL is an important point, but the internal design of each block is also a key issue.