Guillermo Bistué

Eurobalise-Train communication modelling to assess interferences in railway control signalling systems

The evolution of the railway sector depends, to a great extent, on the deployment of advanced railway signalling systems. These signalling systems are based on communication architectures that must cope with complex electromagnetical environments. This paper is outlined in the context of developing the necessary tools to allow the quick deployment of these signalling systems by contributing to an easier analysis of their behaviour under the effect of electromagnetical interferences. Specifically, this paper presents the modelling of the Eurobalise-train communication flow in a general purpose simulation tool. It is critical to guarantee this communication link since any lack of communication may lead to a stop of the train and availability problems. In order to model precisely this communication link we used real measurements done in a laboratory equipped with elements defined in the suitable subsets. Through the simulation study carried out, we obtained performance indicators of the physical layer such as the received power, SNR and BER. The modelling presented in this paper is a required step to be able to provide quality of service indicators related to perturbed scenarios.

Low power RF circuit design in standard CMOS technology

Introduction.- Power Considerations in Analog Rf CMOS Circuits.- Impact of Architecture Selection on RF Front-End Power Consumption.- Technology Structural Alternatives in Standard CMOS Technologies for Low-Power Analog Design.- Schematic Design Techniques for Power Saving in RF.- RF Amplifier Design.- Mixer Design.- Phase Locked Loop (PLL) Design.

Design for test of a low power multi-standard GPS/GALILEO RF front-end

This contribution deals with the complete design of a multi-standard GPS/GALILEO front-end, from setting the specifications through to the complete characterization of the device. Special focus will be given to the design for test and the characterization of the design, as optimizing the time spent on this improves time-to-market for the product under development. The highly integrated, low power GPS/GALILEO front-end is designed with a low-IF architecture. The front-end exhibits a voltage gain of 103dB with a power consumption of 66mW from a 3V voltage supply and 38mW if the internal dual-gain LNA is switched OFF. The SSB noise figure of 3.7dB which makes it suitable for high sensitivity applications. Te implemented architecture allows 3 different configurations, adding flexibility to its future applications.

A high sensitivity and low power envelope detector for wireless sensor nodes

In this paper different parts of a wake-up receiver for wireless sensor node are presented. The circuit is composed of an amplifier with input impedance matching network and an envelope detector both working at 868 MHz. The amplifier is incorporated in order to increase the sensitivity of the wake-up receiver. The amplified signal passes to the envelope detector which demodulate on-off keying signal at 125 kHz. The circuits have been designed to optimize power consumption and area. The total power consumption and the minimum signal detected are 44.32 uW and 0.4 mVp respectively. The circuits were implemented in UMC CMOS 65 nm process.

A CMOS frequency synthesizer with selfbiasing current source for a 5-GHz wireless LAN receiver

In this work, an integrated 3.2 GHz phase locked loop (PLL) with a selfbiasing current source is presented. The circuit has been designed using a 3.3 V 0.18/spl mu/m CMOS technology. The synthesizer consumes 55 mW of which 20 mW is consumed by the VCO. The PLL has a bandwidth of 100 KHz and a phase noise of -111 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -70 dBc. These results made the circuit suitable inside a 5 GHz wireless LAN receiver.

A low power CMOS temperature-to-frequency converter for RFID applications

This paper presents the design of a low power temperature sensor based on temperature-to-frequency conversion for RFID applications. The variation of temperature is detected by a PTC resistor that determines the reference current of a bootstrapped cascode source. This current is used to bias an active inductor. The self-resonance frequency varies accordingly to the shift of the current, thus providing the temperature to frequency conversion. The circuit has been implemented using a standard 65 nm CMOS technology. A frequency of oscillation of 31.3 MHz at 20°C has been obtained, with an estimated sensitivity of 50.5 kHz/°C, a resolution of 0.12°C and a power consumption of 21.8 uW within the 0-80°C temperature range.

RF Amplifier Design

This chapter deals with the design of the basic amplifying stages. It also provides the introductory tools required for the design of any kind of amplifier (VGA, LNA, BUFFERS, etc). Due to its importance for CMOS ICs, the low noise amplifier is deeply studiedi this chapter.

Power Considerations in Analog RF CMOS Circuits

This chapter deals with the basic principles of power consumption in RF CMOS analog circuits. These concepts are used extensively throughout the book; therefore the different sections of the chapter are dedicated to the presentation of general definitions and formulas. Section 2.1 introduces the different sources of power dissipation in analogue circuits, regarding both static and dynamic power dissipation mechanisms, from a steady and transient perspective respectively. Section 2.2 reviews the classical considerations for low power digital circuits and their structures. Then, section 2.3 deals with the power supply scaling as a means to achieve low- power benefits, which is highly related to section 2.2, and finally section 2.3 outlines the practical limits in power consumption from a triple perspective: starting from the front-end architecture and CMOS technology constraints through the RF and analog circuits.

Phase Locked Loop (PLL) Design

The last building block covered in the book is the Phase Locked Loop (PLL), virtually used in every integrated communication front-end. The complexity of this system is high; therefore the first section is dedicated to the basic concepts related to both PLL system architectures and basic components. The architecture of the classical phase locked loops used in RF IC designs are presented in that first section. Nevertheless, from the power consumption point of view, the decision on the architecture of the whole PLL is an important point, but the internal design of each block is also a key issue.

Schematic Design Techniques for Power Saving in RF

RF analog circuits are characterised by the use of relatively simple schemes. This is due to the fact that each component adds some kind of parasitic effects, therefore the design always follows the rule of “less is more”. For this reason, most of power saving techniques widely applied in base band or digital circuits is not suitable for high frequency applications. Chapter 5 outlines the most useful alternatives. In this chapter the general principles are presented, and many references to other works are also included. In order to help the reader to fully understand the impact of these techniques, basic simulations and comparisons are included. The practical application of these techniques is presented in subsequent chapters.