Jeffrey L. Burns

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.

A 1.0-GHz single-issue 64-bit powerPC integer processor

This 64 b single-issue integer processor, comprised of about one million transistors, is fabricated in a 0.15 /spl mu/m effective channel length, six-metal-layer CMOS technology. Intended as a vehicle to explore circuit, clocking, microarchitecture, and methodology options for high-frequency processors, the processor prototype implements 60 fixed-point compare, logical, arithmetic, and rotate-merge-mask instructions of the PowerPC instruction-set architecture with single-cycle latency. The processor executes programs written in this instruction subset from cache with a 1 ns cycle. In addition, the prototype implements 36 PowerPC load/store instructions that execute as single-cycle operations (zero wait cycles) with 1.15 ns latency. Full data forwarding and full at speed scan testing are supported.

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits

Input vector control has been used to minimize the leakage powerconsumption of a circuit in sleep state. In this paper, we presenta novel heuristic for determining a low leakage vector to beapplied to a circuit in sleep state. The heuristic is a greedy searchbased on the controllability of nodes in the circuit and uses thefunctional dependencies among cells in the circuit to guide thesearch. Results on a set of ISCAS and MCNC benchmark circuitsshow that in all cases our heuristic returns a vector having aleakage within 5% of that of the vector obtained using an extensiverandom search, with orders of magnitude improvement incomputational speed.

Design methodology for a 1.0 GHz microprocessor

This paper describes the design methodology used to build an experimental 1.0 GigaHertz PowerPC integer microprocessor at IBMs Austin Research Laboratory. The high frequency requirements dictated the chip composition to be almost entirely custom macros using dynamic circuit techniques. The methodology presented will cover design and verification tools as well as circuit constraints and microarchitecture philosophy. The microarchitecture, circuits and tools were defined by the high frequency requirements of the processor as well as the aggressive design schedule and size of the design team.

Leakage and leakage sensitivity computation for combinational circuits

Leakage power is emerging as a new critical challenge in the design of high performance integrated circuits. Leakage is increasing dramatically with each technology generation and is expected to dominate system power. This paper describes a static (i.e input independent) technique for efficient and accurate leakage estimation. A probabilistic technique is presented to compute the average leakage of combinational circuits. The proposed technique gives accurate results with an average error of only 2% for the ISCAS benchmarks and accurately predict both subthreshold and gate leakage as well as the leakage sensitivities to process and environmental parameters.

Resonant clocking using distributed parasitic capacitance

A resonant clock distribution scheme that dissipates less power than conventional, buffer-driven clock distribution is described. All clock buffers are removed and the clock energy is resonated between integrated inductors and the parasitic capacitance of the local clock network, which form the energy storage elements of an LC VCO. Designed and fabricated in IBMs 0.13 /spl mu/m partially-depleted SOI, measurements show that the resonant clock dissipates 63% less power than a conventional, buffer-driven clock driving the same clock network.

A 0.9 V to 1.95 V dynamic voltage-scalable and frequency-scalable 32 b PowerPC processor

A 32 b PowerPC/spl trade/ system-on-a-chip supporting dynamic voltage supply and dynamic frequency scaling operates from 366 MHz at 1.8 V and 600 mW down to 150 MHz at 1.0 V and 53 mW in a 0.18 /spl mu/m CMOS process. Maximum supply change without PLL relock is 10 mV//spl mu/s. Processor state save/restore enables a deep-sleep state.

Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies

Leakage current is becoming an increasingly important fraction of the total power dissipation of integrated circuits. This work focuses on leakage power minimization in light of the growing significance of gate leakage current. The need to consider gate leakage while determining the sleep-state pattern is demonstrated. Circuit reorganization and sleep-state assignment techniques are presented for gate and total leakage minimization of static and dynamic circuits. We also re-evaluate the MTCMOS circuit scheme for total leakage minimization.

A semi-custom voltage-island technique and its application to high-speed serial links

Supply-voltage reduction is a known technique for reducing CMOS active power. We propose a semi-custom voltage-island approach based on internal regulation and selective custom design. This approach enables transparent embedding, since no additional external power supply is needed. We apply the approach to high-speed serial links, and we show that high performance is retained through targeted application of custom circuit and logic design. A chip is presented that evaluates the presented approach on a 3000-gate 3.2-Gbps multi-protocol serial-link receiver logic core. When reducing the supply from 1.2V to 0.95V, the chip demonstrates power savings of over 25%.

Performance driven synthesis for pass-transistor logic

For many digital designs, implementation in pass-transistor logic (PTL) has been shown to be superior in terms of area, timing, and power characteristics to static CMOS. Binary Decision Diagrams (BDDs) have been used for PTL synthesis because of the close relationship between BDDs and PTL. Thus far BDD optimization for PTL synthesis has targeted minimizing the number of BDD nodes. This strategy leads to smaller PTL implementations, but it can result in circuits of poor performance. In this paper we model the delay of PTL circuits derived from BDDs, and propose procedures to reduce the worst-case delay or the area-delay product of such circuits. The experimental results show a significant improvement in the delay (30%) or area-delay product (24%) for the ISCAS benchmark circuits.