Uwe Paul Schroeder

Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for 10nm technology nodes and beyond

A pattern-based methodology for optimizing Self-Aligned Double Patterning (SADP)-compliant layout designs is developed based on detecting cut-induced hotspot patterns and replacing them with pre-characterized fixing solutions. A pattern library with predetermined fixing solutions is built. A pattern-based engine searches for matching patterns in the layout designs. When a match is found, the engine opportunistically replaces the detected pattern with a pre-characterized fixing solution, preserving only the design rule check-clean replacements. The methodology is demonstrated on a 10nm routed block. A small library of fourteen patterns reduced the number of cut-induced design rule check violations by 100% and lithography hotspots by 23%.

EUV and optical lithographic pattern shift at the 5nm node

At the 5 nm technology node there are competing strategies for patterning: high-NA EUV, double patterning 0.33 NA EUV and a combination of optical self-aligned solutions with EUV. This paper investigates the impact of pattern shift based on the selected patterning strategy. A logic standard cell connection between TS and M0 is simulated to determine the impact of lithographic pattern shift on the overlay budget. At 5 nm node dimensions, high-NA EUV is necessary to expose the most critical layers with a single lithography exposure. The impact of high-NA EUV lithography is illustrated by comparing the pattern shift resulting from 0.33 NA vs. 0.5x NA. For the example 5 nm transistor, cost-beneficial lithography layers are patterned with EUV and the other layers are patterned optically. Both EUV and optical lithography simulations are performed to determine the maximum net pattern shift. Here, lithographic pattern shift is quantified in terms of through-focus error as well as pattern-placement error. The overlay error associated with a hybrid optical/self-aligned and EUV cut patterning scheme is compared with the results of an all EUV solution, providing an assessment of two potential patterning solutions and their impact the overall overlay budget.

Methodology to extract, data mine and score geometric constructs from physical design layouts for analysis and applications in semiconductor manufacturing

At advanced technology nodes (sub-22 nm), design rules become very complicated as interactions between multiple layers become more complex, while the number of design elements within the optical radius increases. As a result, one may possibly encounter novel yield limiters in the 2D/3D design space with every new product taping out to the fab. Key to fast yield ramp is identifying novel constructs that may become yield detractors, and to address the challenge in the DFM space before actual Silicon is run. A comprehensive methodology to find such geometric constructs is proposed.

Litho friendly via insertion with in-design auto-fix flow using machine learning

Via failure has always been a significant yield detractor caused by random and systematic defects. Introducing redundant vias or via bars into the design can alleviate the problem significantly [1] and has, therefore, become a standard DFM procedure [2]. Applying rule-based via bar insertion to convert millions of via squares to via bar rectangles, in all possible places where enough room could be predicted, is an efficient methodology to maximize the redundancy rate. However, inserting via bars can result in lithography hotspots. A Pattern Manufacturability (PATMAN) model is proposed, to maximize the Redundant Via Insertion (RVI) rate in a reasonable runtime, while insuring lithography friendly insertion based on the accumulated DFM learnings during the yield ramp.

Quantifying electrical impacts on redundant wire insertion in 7nm unidirectional designs

In nano-meter scale Integrated Circuits, via fails due to random defects is a well-known yield detractor, and via redundancy insertion is a common method to help enhance semiconductors yield. For the case of Self Aligned Double Patterning (SADP), which might require unidirectional design layers as in the case of some advanced technology nodes, the conventional methods of inserting redundant vias don’t work any longer. This is because adding redundant vias conventionally requires adding metal shapes in the non-preferred direction, which will violate the SADP design constraints in that case. Therefore, such metal layers fabricated using unidirectional SADP require an alternative method for providing the needed redundancy. This paper proposes a post-layout Design for Manufacturability (DFM) redundancy insertion method tailored for the design requirements introduced by unidirectional metal layers. The proposed method adds redundant wires in the preferred direction - after searching for nearby vacant routing tracks - in order to provide redundant paths for electrical signals. This method opportunistically adds robustness against failures due to silicon defects without impacting area or incurring new design rule violations. Implementation details of this redundancy insertion method will be explained in this paper. One known challenge with similar DFM layout fixing methods is the possible introduction of undesired electrical impact, causing other unintentional failures in design functionality. In this paper, a study is presented to quantify the electrical impacts of such redundancy insertion scheme and to examine if that electrical impact can be tolerated. The paper will show results to evaluate DFM insertion rates and corresponding electrical impact for a given design utilization and maximum inserted wire length. Parasitic extraction and static timing analysis results will be presented. A typical digital design implemented using GLOBALFOUNDRIES 7nm technology is used for demonstration. The provided results can help evaluate such extensive DFM insertion method from an electrical standpoint. Furthermore, the results could provide guidance on how to implement the proposed method of adding electrical redundancy such that intolerable electrical impacts could be avoided.

Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for sub-20nm metal routing

A pattern-based methodology for optimizing SADP-compliant layout designs is developed based on identifying cut mask patterns and replacing them with pre-characterized fixing solutions. A pattern-based library of difficult-tomanufacture cut patterns with pre-characterized fixing solutions is built. A pattern-based engine searches for matching patterns in the decomposed layouts. When a match is found, the engine opportunistically replaces the detected pattern with a pre-characterized fixing solution. The methodology was demonstrated on a 7nm routed metal2 block. A small library of 30 cut patterns increased the number of more manufacturable cuts by 38% and metal-via enclosure by 13% with a small parasitic capacitance impact of 0.3%.

Hybrid pattern matching based SRAF placement

A hybrid multi-step method for Sub-Resolution Assist Feature (SRAF) placement is presented. The process window, characterized by process variation bands (PV-bands), is subjected to optimization. By applying a state-of-the-art advanced pattern matching based approach, the SRAF placement is optimized to maximize the process window. Due to the complexity of building a complete Rule-Based SRAF (RBSRAF) solution and the performance limitation of the Model-Based SRAF solution (MBSRAF), the hybrid pattern based SRAF reduces the complexity and improves performance. In this paper, the hybrid pattern-based SRAF algorithm and its implementation, as well as testing results, are discussed with respect to process window and performance.