Lynn T.-N. Wang

Framework for identifying recommended rules and DFM scoring model to improve manufacturability of sub-20nm layout design

This paper addresses the framework for building critical recommended rules and a methodology for devising scoring models using simulation or silicon data. Recommended rules need to be applied to critical layout configurations (edge or polygon based geometric relations), which can cause yield issues depending on layout context and process variability. Determining of critical recommended rules is the first step for this framework. Based on process specifications and design rule calculations, recommended rules are characterized by evaluating the manufacturability response to improvements in a layout-dependent parameter. This study is applied to critical 20nm recommended rules. In order to enable the scoring of layouts, this paper also discusses a CAD framework involved in supporting use-models for improving the DFM-compliance of a physical design.

Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for 10nm technology nodes and beyond

A pattern-based methodology for optimizing Self-Aligned Double Patterning (SADP)-compliant layout designs is developed based on detecting cut-induced hotspot patterns and replacing them with pre-characterized fixing solutions. A pattern library with predetermined fixing solutions is built. A pattern-based engine searches for matching patterns in the layout designs. When a match is found, the engine opportunistically replaces the detected pattern with a pre-characterized fixing solution, preserving only the design rule check-clean replacements. The methodology is demonstrated on a 10nm routed block. A small library of fourteen patterns reduced the number of cut-induced design rule check violations by 100% and lithography hotspots by 23%.

Pattern matching for identifying and resolving non-decomposition-friendly designs for double patterning technology (DPT)

A pattern matching methodology that identifies non-decomposition-friendly designs and provides localized guidance for layout-fixing is presented for double patterning lithography. This methodology uses a library of patterns in which each pattern has been pre-characterized as impossible-to-decompose and annotated with a design rule for guiding the layout fixes. A pattern matching engine identifies these problematic patterns in design, which allows the layout designers to anticipate and prevent decomposition errors, prior to layout decomposition. The methodology has been demonstrated on a 180 um2 layout migrated from the previous 28nm technology node for the metal 1 layer. Using a small library of just 18 patterns, the pattern matching engine identified 119 out of 400 decomposition errors, which constituted coverage of 29.8%.

Decomposition-aware layout optimization for 20/14nm standard cells

Decomposition-aware layout design improvements for 8, 9, 11, and 13-track 20/14nm standard cells are presented. Using a decomposition-aware scoring methodology that quantifies the manufacturability of layouts, the Double Patterning Technology (DPT)-compliant layouts are optimized for DPT-specific metrics that include: the density difference between the two decomposition mask layers, the enclosure of stitching areas, the density of stitches, and the design regularity of stitching areas. For a 9-track standard cell, eliminating the stitches from the layout design improved the composite score from 0.53 to 0.70.

Post-decomposition optimizations using pattern matching and rule-based clustering for multi-patterning technology

A pattern matching and rule-based polygon clustering methodology with DFM scoring is proposed to detect decomposition-induced manufacturability detractors and fix the layout designs prior to manufacturing. A pattern matcher scans the layout for pre-characterized patterns from a library. If a pattern were detected, rule-based clustering identifies the neighboring polygons that interact with those captured by the pattern. Then, DFM scores are computed for the possible layout fixes: the fix with the best score is applied. The proposed methodology was applied to two 20nm products with a chip area of 11 mm2 on the metal 2 layer. All the hotspots were resolved. The number of DFM spacing violations decreased by 7-15%.

Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for sub-20nm metal routing

A pattern-based methodology for optimizing SADP-compliant layout designs is developed based on identifying cut mask patterns and replacing them with pre-characterized fixing solutions. A pattern-based library of difficult-tomanufacture cut patterns with pre-characterized fixing solutions is built. A pattern-based engine searches for matching patterns in the decomposed layouts. When a match is found, the engine opportunistically replaces the detected pattern with a pre-characterized fixing solution. The methodology was demonstrated on a 7nm routed metal2 block. A small library of 30 cut patterns increased the number of more manufacturable cuts by 38% and metal-via enclosure by 13% with a small parasitic capacitance impact of 0.3%.

A pattern-based methodology for optimizing stitches in double-patterning technology

A pattern-based methodology for optimizing stitches is developed based on identifying stitch topologies and replacing them with pre-characterized fixing solutions in decomposed layouts. A topology-based library of stitches with predetermined fixing solutions is built. A pattern-based engine searches for matching topologies in the decomposed layouts. When a match is found, the engine opportunistically replaces the predetermined fixing solution: only a design rule check error-free replacement is preserved. The methodology is demonstrated on a 20nm layout design that contains over 67 million, first metal layer stitches. Results show that a small library containing 3 stitch topologies improves the stitch area regularity by 4x.

A scoring methodology for quantitatively evaluating the quality of double patterning technology-compliant layouts

A Double Patterning Technology (DPT)-aware scoring methodology that systematically quantifies the quality of DPTcompliant layout designs is described. The methodology evaluates layouts based on a set of DPT-specific metrics that characterizes layout-induced process variation. Specific metrics include: the spacing variability between two adjacent oppositely-colored features, the density differences between the two exposure masks, and the stitching areas sensitivity to mask misalignment. These metrics are abstracted to a scoring scale from 0 to 1 such that 1 is the optimum. This methodology provides guidance for opportunistic layout modifications so that DPT manufacturability-related issues are mitigated earlier in design. Results show that by using this methodology, a DPT-compliant layout improved from a composite score of 0.66 and 0.78 by merely changing the decomposition solution so that the density distribution between the two exposure masks is relatively equal.