Piyush Pathak

Framework for identifying recommended rules and DFM scoring model to improve manufacturability of sub-20nm layout design

This paper addresses the framework for building critical recommended rules and a methodology for devising scoring models using simulation or silicon data. Recommended rules need to be applied to critical layout configurations (edge or polygon based geometric relations), which can cause yield issues depending on layout context and process variability. Determining of critical recommended rules is the first step for this framework. Based on process specifications and design rule calculations, recommended rules are characterized by evaluating the manufacturability response to improvements in a layout-dependent parameter. This study is applied to critical 20nm recommended rules. In order to enable the scoring of layouts, this paper also discusses a CAD framework involved in supporting use-models for improving the DFM-compliance of a physical design.

Automated yield enhancements implementation on full 28nm chip: challenges and statistics

This paper shares the details of the Yield Enhancements that were done at 28nm full chip level sharing the complexity involved in implementing such a flow and then the verification challenges involved , e.g., at mask data preparation. We discuss and present the algorithm used to measure the efficiency of the tool, explaining why we used this algorithm while sharing some alternate algorithms possible. We also share the detailed statistics regarding run time, machine resource, data size, polygon counts etc. We also present good techniques used by us for efficient flow management involved in large complex 28nm chips.

Methodology to extract, data mine and score geometric constructs from physical design layouts for analysis and applications in semiconductor manufacturing

At advanced technology nodes (sub-22 nm), design rules become very complicated as interactions between multiple layers become more complex, while the number of design elements within the optical radius increases. As a result, one may possibly encounter novel yield limiters in the 2D/3D design space with every new product taping out to the fab. Key to fast yield ramp is identifying novel constructs that may become yield detractors, and to address the challenge in the DFM space before actual Silicon is run. A comprehensive methodology to find such geometric constructs is proposed.

Hybrid OPC flow with pattern search and replacement

Optical Proximity Correction (OPC) is a compute-intensive process used to generate photolithography mask shapes at advanced VLSI nodes. Previously, we reported a modified two-step OPC flow which consists of a first pattern replacement step followed by a model based OPC correction step [1]. We build on this previous work and show how this hybrid flow not only improves full chip OPC runtime, but also significantly improves mask correction consistency and overall mask quality. This is demonstrated using a design from the 20nm node, which requires the use of model based SRAF followed by model based OPC to obtain the full mask solution.

A methodology to optimize design pattern context size for higher sensitivity to hotspot detection using pattern association tree (PAT)

Pattern based design rule checks have emerged as an alternative to the traditional rule based design rule checks in the VLSI verification flow [1]. Typically, the design-process weak-points, also referred as design hotspots, are classified into patterns of fixed size. The size of the pattern defines the radius of influence for the process. These fixed sized patterns are used to search and detect process weak points in new designs without running computationally expensive process simulations. However, both the complexity of the pattern and different kinds of physical processes affect the radii of influence. Therefore, there is a need to determine the optimal pattern radius (size) for efficient hotspot detection. The methodology described here uses a combination of pattern classification and pattern search techniques to create a directed graph, referred to as the Pattern Association Tree (PAT). The pattern association tree is then filtered based on the relevance, sensitivity and context area of each pattern node. The critical patterns are identified by traversing the tree and ranking the patterns. This method has plausible applications in various areas such as process characterization, physical design verification and physical design optimization. Our initial experiments in the area of physical design verification confirm that a pattern deck with the radius optimized for each pattern is significantly more accurate at predicting design hotspots when compared to a conventional deck of fixed sized patterns.

Smart double-cut via insertion flow with dynamic design-rules compliance for fast new technology adoption

As IC technologies shrink and via defects remain the same size, the probability of via defects increases. Redundant via insertion is an effective method to reduce yield loss related to via failures, but a large number of extremely complex design rules make efficient automatic via insertion difficult. This paper introduces an automatic redundant via insertion flow which is capable of adopting new technologies and complex design rules extremely quickly. Runtime and efficiency are optimized through a smart insertion scheduling technique. Our experiments show that it efficiently improves redundant via percentage, making designs more robust against via defects.

A scoring methodology for quantitatively evaluating the quality of double patterning technology-compliant layouts

A Double Patterning Technology (DPT)-aware scoring methodology that systematically quantifies the quality of DPTcompliant layout designs is described. The methodology evaluates layouts based on a set of DPT-specific metrics that characterizes layout-induced process variation. Specific metrics include: the spacing variability between two adjacent oppositely-colored features, the density differences between the two exposure masks, and the stitching areas sensitivity to mask misalignment. These metrics are abstracted to a scoring scale from 0 to 1 such that 1 is the optimum. This methodology provides guidance for opportunistic layout modifications so that DPT manufacturability-related issues are mitigated earlier in design. Results show that by using this methodology, a DPT-compliant layout improved from a composite score of 0.66 and 0.78 by merely changing the decomposition solution so that the density distribution between the two exposure masks is relatively equal.

Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs

We identify most recent sources of transistor layout dependent effects (LDE) such as stress, lithography, and well proximity effects (WPE), and outline modeling and analysis methods for 28 nm. These methods apply to custom layout, standard cell designs, and context-aware post-route analysis. We show how IC design teams can use a model-based approach to quantify and analyze variability induced by LDE. We reduce the need for guard-bands that negate the performance advantages that stress brings to advanced process technologies.