Uwe Sparmann

On the effectiveness of residue code checking for parallel two's complement multipliers

The effectiveness of residue code checking for on-line error detection in parallel twos complement multipliers has up to now only been evaluated experimentally for few architectures. In this paper a formal analysis is given for most of the current multiplication schemes. Based on this analysis it is shown which check bases are appropriate, and how the original scheme has to be extended for complete error detection at the input registers and Booth recording circuitry. In addition, we argue that the hardware overhead for checking can be reduced by approximately one half if a small latency in error detection is acceptable. Schemes for structuring the checking logic in order to guarantee it to be self-testing, and thus achieve the totally self-checking goal for the overall circuit, are also derived.<<ETX>>

Universal delay test sets for logic networks

It has been shown earlier that, if we are restricted to unate gate network (UGN) realizations, there exist universal test sets for Boolean functions. Such a test set only depends on the function f, and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper, we prove that these universal test sets are much more powerful than implied by the above results. They also constitute complete delay fault test sets for arbitrary UGN implementations of a given function. This is even true for UGN networks which are not completely testable with respect to the gate or path delay fault model. Our ability to prove the temporal correctness of such circuit realizations comes from the fact that we do not argue the correctness of individual paths, but rather complete path systems.

Computations over finite monoids and their test complexity

The authors consider the test pattern generation problem for circuits than compute expressions over some algebraic structure. The relation between the algebraic properties of this structure and its test complexity is analyzed. This relation is looked at in detail for the family of all finite monoids. The test complexity of a monoid with respect to a problem is measured by the number of tests needed to check the best testable circuit (in a certain computational model) that will solve the problem. Two important computations over finite monoids, namely, expression evaluation and parallel prefix computation, are considered. In both cases it can be shown that the set of all finite monoids partitions into exactly three classes with constant, logarithmic, and linear test complexity, respectively. These classes are characterized using algebraic properties. For each class, circuits are provided with optimal test sets and efficient methods, which decide the membership problem for a given finite monoid M.<<ETX>>

Structure based methods for parallel pattern fault simulation in combinational circuits

The authors present several methods which accelerate fault simulation for combinational circuits using parallel pattern evaluation. The methods are based on an extensive structure analysis of the considered circuit. On the one hand the developed methods aim at a reduction of fan-out stems for which the fault simulation has to be performed and on the other hand at a reduction of gate evaluations during the fault simulation. Of course, all methods support the use of parallel pattern evaluation.<<ETX>>

Regular Structures and Testing: RCC-Adders

We confine ourselves to one of the basic problems of testing, the test pattern generation problem for combinational circuits, and study the relation between structural properties and test complexity.

Derivation of high quality tests for large heterogeneous circuits: floating-point operations

The problem of deriving high quality tests for fast combinational floating-point realizations is investigated. Floating-point circuits are heterogeneous, consisting of a large number of regular and irregular modules. Thus, the test strategy applied combines specialized structure based methods and universal test generation. In order to guarantee sufficient controllability and observability of embedded modules, small hardware modifications are proposed. As a result, the authors obtain optimal-time floating-point circuits for arbitrary operand lengths which can be tested completely with respect to a strong fault model by a minimal number of test patterns.<<ETX>>

On the testability of iterative logic arrays

Abstract The problem of detecting single cellular faults in arbitrarily large one-dimensional, unilateral, combinational iterative logic array (= ILAs) is considered. Fault patterns (= FPs) of the ILAs basic cell are introduced to characterize any cellular fault. Testability properties like (full, partial) testability, redundancy, test complexity of FPs are studied. Based on this analysis we prove that only two test complexity classes exist: the minimum size of a complete test set of an ILA is either constant—in this case the ILA is called C-testable — or linear in the length of the ILA. Furthermore, depending on the type of the FP that is considered new efficient algorithms for the determination of the test complexity and the construction of complete test sets are presented. In particular, we reduce the exponential worst case complexity of the construction given in (Friedman, 1973) to a polynomial worst case bound (measured in the size of the function table for the basic cell).

Local transformations and robust dependent path delay faults

Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speech, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct timing behavior. For example, a set of robust dependent path delay faults need not be considered for testing if all paths that are not robust dependent are tested. We present sufficient conditions for local transformations which ensure that a test set for all non-robust-dependent paths in the original circuit is also a test set for all non-robust-dependent paths in the transformed circuit. These conditions are applied to some local transformations which are often used in logic synthesis and it is shown that they preserve testability. The impact of local transformations on robust dependent testability is demonstrated by experimental results performed on benchmark circuits.

Two-layer wiring with pin preassignments is easier if the power supply nets are already generated

We examine the constrained via minimization problem with pin preassignments (CVMPP) which arises in connection with hierarchical physical synthesis. Let A be a circuit composed of subcircuits B, C, D,.... Assume that the placement and routing phase together with the 2-layer wiring of the subcircuits, and the placement and routing phase without the 2-layer wiring of A are completed. CVMPP is the problem of finding a 2-layer wiring /spl deltasub A/ of A which is induced by the 2-layer wirings of the subcircuits and which contains a minimal amount of vias on this condition. First, we show that CVMPP is NP-hard. In the case that the wiring of the power supply nets has already been generated we present a polynomial time algorithm solving CVMPP.<<ETX>>