Harry Hengster

Testability of 2-level AND/EXOR circuits

It is often stated that AND/EXOR circuits are much easier to test than AND/OR circuits. This statement, however, only holds true for circuits derived from restricted classes of AND/EXOR expressions, like positive polarity Reed-Muller and fixed polarity Reed-Muller expressions. For these two classes of expressions, circuits with good deterministic testability properties are known. In this paper we show that these circuits also have good random pattern testability attributes. An input probability distribution is given that yields a short expected test length for biased random patterns. This is the first time theoretical results on random pattern testability are presented for 2-level AND/EXOR circuit realizations of arbitrary Boolean functions. It turns out that analogous results cannot be expected for less restricted classes of 2-level AND/EXOR circuits. We present experiments demonstrating that generally minimized 2-level AND/OR circuits can be tested as easy (or hard) as minimized 2-level AND/EXOR circuits.

Testability properties of local circuit transformations with respect to the robust path-delay-fault model

We present a new approach to show that local circuit transformations which improve the area of a circuit preserve or improve robust path-delay-fault testability. In contrast to previously published methods which had to consider the whole circuit we examine only the subcircuits to be transformed. Furthermore, we present some new transformations which preserve or improve robust path-delay-fault testability.<<ETX>>

A scalable BIST architecture for delay faults

We present a scalable BIST (Built-In Self Test) architecture that provides a tunable trade-off between on-chip area demand and test execution time for delay fault testing. So, the architecture can meet test execution time requirements, area requirements, or any target in between. Experiments show the scalability of our approach, e.g., that considerably shorter test execution time can be achieved by storing only a few additional input vectors of the BIST architecture. The gain of test execution time possible with the proposed method ranges from a factor of 2 up to a factor of more than 800000.

On local transformations and path delay fault testability

Several synthesis for path delay fault (PDF) testability approaches are based on local transformations of digital circuits. Different methods were used to show that transformations preserve or improve PDF testability. In this paper we present a new unifying approach to show that local transformations preserve or improve PDF testability. This approach can be applied to every local transformation and in contrast to previously published methods only the subcircuits to be transformed have to be considered.Using our new approach we are able to show in a very convenient way that the transformations which are already used in synthesis tools preserve or improve PDF testability. We present further transformations which preserve or improve testability. We show that a transformation, claimed to preserve PDF testability, in fact, does not do so. Moreover, the testability improving factor which is a unit of measurement for the quality of testability improving transformations is introduced.Additionally, we present the capabilities of SALT (system forapplication oflocaltransformations), which is a general tool for application of a predefined set of local transformations. The implementation of SALT is described and it is shown how the isomorphism of a “pattern to be searched” and a “matched subcircuit” can be weakened to allow the application of local transformations more frequently.Finally, we confirm the theoretical part of this paper by experimental results obtained by application of the examined local transformations to several benchmark circuits. The effect of these transformations (and combinations of different types of transformations) on PDF testability, size and depth of the transformed circuits is examined and encouraging results are presented. For example, a reduction of up to 90% can be observed for the number of untestable paths.

AND/EXOR-based synthesis of testable KFDD-circuits with small depth

Decision Diagrams are used in design automation for efficient representation of Boolean functions. It is also possible to directly derive circuits from Decision Diagrams. In this paper we present an approach to synthesize circuits from a very general class of Decision Diagrams, the ordered Kronecker Functional Decision Diagrams. These Decision Diagrams make use of Davio decompositions which are based on exclusive-or operations and therefore allow the use of EXOR gates in the synthesized circuits. We investigate area, depth, and testability of these circuits and compare them to circuit designs generated by other synthesis tools. Experimental results show that the presented approach is suitable to overcome the trade-off between depth and testability at the price of reasonable area overhead.

On the application of local circuit transformations with special emphasis on path delay fault testability

Several types of local transformations and their effect on path delay fault testability have been examined in the literature. In this paper we present SALT (System for Application of Local Transformations), which is a general tool for the application of a user-defined set of local transformations. The concepts of related transformations and of pseudo-isomorphism are introduced, which are used in SALT to allow the application of local transformations more frequently. We use SALT to apply testability preserving and testability improving transformations. The effect of these transformations on the size, depth and testability of the transformed circuits is compared to the results obtained by other approaches on benchmark circuits.

Local transformations and robust dependent path delay faults

Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speech, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct timing behavior. For example, a set of robust dependent path delay faults need not be considered for testing if all paths that are not robust dependent are tested. We present sufficient conditions for local transformations which ensure that a test set for all non-robust-dependent paths in the original circuit is also a test set for all non-robust-dependent paths in the transformed circuit. These conditions are applied to some local transformations which are often used in logic synthesis and it is shown that they preserve testability. The impact of local transformations on robust dependent testability is demonstrated by experimental results performed on benchmark circuits.

Synthesis of circuits derived from decision diagrams-combining small delay and testability

We present a synthesis for testability approach to obtain EXOR-based circuits with inherently small delay. The starting point of our approach is a functional specification given in form of a so-called Kronecker Functional Decision Diagram (KFDD). The KFDD is transformed into a circuit by using a composition method based on Boolean matrix multiplication. Efficient algorithms working on the KFDD are applied during synthesis to avoid the creation of constant lines. Thereby first stuck-at fault testability is guaranteed by construction. Moreover tests for all faults can be derived efficiently from the graph of the KFDD. Thus, it is not necessary to apply automatic test pattern generation (ATPG) to compute test sets for the synthesized circuits or to check for redundancies. Area and delay of the circuits can be further improved by merging of equivalent gates. Altogether our approach makes it possible to combine high speed with fill testability for circuits derived from KFDDs. Finally, the efficiency of the proposed methods is demonstrated by experiments.